SDcardBootloader  0
bootloader for stm32f405 (adafruit's feather express) SD card based
stm32f405xx.h
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1 
33 #ifndef __STM32F405xx_H
34 #define __STM32F405xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
47 #define __CM4_REV 0x0001U
48 #define __MPU_PRESENT 1U
49 #define __NVIC_PRIO_BITS 4U
50 #define __Vendor_SysTickConfig 0U
51 #define __FPU_PRESENT 1U
65 typedef enum
66 {
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68  NonMaskableInt_IRQn = -14,
69  MemoryManagement_IRQn = -12,
70  BusFault_IRQn = -11,
71  UsageFault_IRQn = -10,
72  SVCall_IRQn = -5,
73  DebugMonitor_IRQn = -4,
74  PendSV_IRQn = -2,
75  SysTick_IRQn = -1,
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
77  WWDG_IRQn = 0,
78  PVD_IRQn = 1,
79  TAMP_STAMP_IRQn = 2,
80  RTC_WKUP_IRQn = 3,
81  FLASH_IRQn = 4,
82  RCC_IRQn = 5,
83  EXTI0_IRQn = 6,
84  EXTI1_IRQn = 7,
85  EXTI2_IRQn = 8,
86  EXTI3_IRQn = 9,
87  EXTI4_IRQn = 10,
88  DMA1_Stream0_IRQn = 11,
89  DMA1_Stream1_IRQn = 12,
90  DMA1_Stream2_IRQn = 13,
91  DMA1_Stream3_IRQn = 14,
92  DMA1_Stream4_IRQn = 15,
93  DMA1_Stream5_IRQn = 16,
94  DMA1_Stream6_IRQn = 17,
95  ADC_IRQn = 18,
96  CAN1_TX_IRQn = 19,
97  CAN1_RX0_IRQn = 20,
98  CAN1_RX1_IRQn = 21,
99  CAN1_SCE_IRQn = 22,
100  EXTI9_5_IRQn = 23,
101  TIM1_BRK_TIM9_IRQn = 24,
102  TIM1_UP_TIM10_IRQn = 25,
103  TIM1_TRG_COM_TIM11_IRQn = 26,
104  TIM1_CC_IRQn = 27,
105  TIM2_IRQn = 28,
106  TIM3_IRQn = 29,
107  TIM4_IRQn = 30,
108  I2C1_EV_IRQn = 31,
109  I2C1_ER_IRQn = 32,
110  I2C2_EV_IRQn = 33,
111  I2C2_ER_IRQn = 34,
112  SPI1_IRQn = 35,
113  SPI2_IRQn = 36,
114  USART1_IRQn = 37,
115  USART2_IRQn = 38,
116  USART3_IRQn = 39,
117  EXTI15_10_IRQn = 40,
118  RTC_Alarm_IRQn = 41,
119  OTG_FS_WKUP_IRQn = 42,
120  TIM8_BRK_TIM12_IRQn = 43,
121  TIM8_UP_TIM13_IRQn = 44,
122  TIM8_TRG_COM_TIM14_IRQn = 45,
123  TIM8_CC_IRQn = 46,
124  DMA1_Stream7_IRQn = 47,
125  FSMC_IRQn = 48,
126  SDIO_IRQn = 49,
127  TIM5_IRQn = 50,
128  SPI3_IRQn = 51,
129  UART4_IRQn = 52,
130  UART5_IRQn = 53,
131  TIM6_DAC_IRQn = 54,
132  TIM7_IRQn = 55,
133  DMA2_Stream0_IRQn = 56,
134  DMA2_Stream1_IRQn = 57,
135  DMA2_Stream2_IRQn = 58,
136  DMA2_Stream3_IRQn = 59,
137  DMA2_Stream4_IRQn = 60,
138  CAN2_TX_IRQn = 63,
139  CAN2_RX0_IRQn = 64,
140  CAN2_RX1_IRQn = 65,
141  CAN2_SCE_IRQn = 66,
142  OTG_FS_IRQn = 67,
143  DMA2_Stream5_IRQn = 68,
144  DMA2_Stream6_IRQn = 69,
145  DMA2_Stream7_IRQn = 70,
146  USART6_IRQn = 71,
147  I2C3_EV_IRQn = 72,
148  I2C3_ER_IRQn = 73,
149  OTG_HS_EP1_OUT_IRQn = 74,
150  OTG_HS_EP1_IN_IRQn = 75,
151  OTG_HS_WKUP_IRQn = 76,
152  OTG_HS_IRQn = 77,
153  RNG_IRQn = 80,
154  FPU_IRQn = 81
155 } IRQn_Type;
156 /* Legacy define */
157 #define HASH_RNG_IRQn RNG_IRQn
158 
163 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
164 #include "system_stm32f4xx.h"
165 #include <stdint.h>
166 
175 typedef struct
176 {
177  __IO uint32_t SR;
178  __IO uint32_t CR1;
179  __IO uint32_t CR2;
180  __IO uint32_t SMPR1;
181  __IO uint32_t SMPR2;
182  __IO uint32_t JOFR1;
183  __IO uint32_t JOFR2;
184  __IO uint32_t JOFR3;
185  __IO uint32_t JOFR4;
186  __IO uint32_t HTR;
187  __IO uint32_t LTR;
188  __IO uint32_t SQR1;
189  __IO uint32_t SQR2;
190  __IO uint32_t SQR3;
191  __IO uint32_t JSQR;
192  __IO uint32_t JDR1;
193  __IO uint32_t JDR2;
194  __IO uint32_t JDR3;
195  __IO uint32_t JDR4;
196  __IO uint32_t DR;
197 } ADC_TypeDef;
198 
199 typedef struct
200 {
201  __IO uint32_t CSR;
202  __IO uint32_t CCR;
203  __IO uint32_t CDR;
205 } ADC_Common_TypeDef;
206 
207 
212 typedef struct
213 {
214  __IO uint32_t TIR;
215  __IO uint32_t TDTR;
216  __IO uint32_t TDLR;
217  __IO uint32_t TDHR;
218 } CAN_TxMailBox_TypeDef;
219 
224 typedef struct
225 {
226  __IO uint32_t RIR;
227  __IO uint32_t RDTR;
228  __IO uint32_t RDLR;
229  __IO uint32_t RDHR;
230 } CAN_FIFOMailBox_TypeDef;
231 
236 typedef struct
237 {
238  __IO uint32_t FR1;
239  __IO uint32_t FR2;
240 } CAN_FilterRegister_TypeDef;
241 
246 typedef struct
247 {
248  __IO uint32_t MCR;
249  __IO uint32_t MSR;
250  __IO uint32_t TSR;
251  __IO uint32_t RF0R;
252  __IO uint32_t RF1R;
253  __IO uint32_t IER;
254  __IO uint32_t ESR;
255  __IO uint32_t BTR;
256  uint32_t RESERVED0[88];
257  CAN_TxMailBox_TypeDef sTxMailBox[3];
258  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
259  uint32_t RESERVED1[12];
260  __IO uint32_t FMR;
261  __IO uint32_t FM1R;
262  uint32_t RESERVED2;
263  __IO uint32_t FS1R;
264  uint32_t RESERVED3;
265  __IO uint32_t FFA1R;
266  uint32_t RESERVED4;
267  __IO uint32_t FA1R;
268  uint32_t RESERVED5[8];
269  CAN_FilterRegister_TypeDef sFilterRegister[28];
270 } CAN_TypeDef;
271 
276 typedef struct
277 {
278  __IO uint32_t DR;
279  __IO uint8_t IDR;
280  uint8_t RESERVED0;
281  uint16_t RESERVED1;
282  __IO uint32_t CR;
283 } CRC_TypeDef;
284 
289 typedef struct
290 {
291  __IO uint32_t CR;
292  __IO uint32_t SWTRIGR;
293  __IO uint32_t DHR12R1;
294  __IO uint32_t DHR12L1;
295  __IO uint32_t DHR8R1;
296  __IO uint32_t DHR12R2;
297  __IO uint32_t DHR12L2;
298  __IO uint32_t DHR8R2;
299  __IO uint32_t DHR12RD;
300  __IO uint32_t DHR12LD;
301  __IO uint32_t DHR8RD;
302  __IO uint32_t DOR1;
303  __IO uint32_t DOR2;
304  __IO uint32_t SR;
305 } DAC_TypeDef;
306 
311 typedef struct
312 {
313  __IO uint32_t IDCODE;
314  __IO uint32_t CR;
315  __IO uint32_t APB1FZ;
316  __IO uint32_t APB2FZ;
317 }DBGMCU_TypeDef;
318 
319 
324 typedef struct
325 {
326  __IO uint32_t CR;
327  __IO uint32_t NDTR;
328  __IO uint32_t PAR;
329  __IO uint32_t M0AR;
330  __IO uint32_t M1AR;
331  __IO uint32_t FCR;
332 } DMA_Stream_TypeDef;
333 
334 typedef struct
335 {
336  __IO uint32_t LISR;
337  __IO uint32_t HISR;
338  __IO uint32_t LIFCR;
339  __IO uint32_t HIFCR;
340 } DMA_TypeDef;
341 
346 typedef struct
347 {
348  __IO uint32_t IMR;
349  __IO uint32_t EMR;
350  __IO uint32_t RTSR;
351  __IO uint32_t FTSR;
352  __IO uint32_t SWIER;
353  __IO uint32_t PR;
354 } EXTI_TypeDef;
355 
360 typedef struct
361 {
362  __IO uint32_t ACR;
363  __IO uint32_t KEYR;
364  __IO uint32_t OPTKEYR;
365  __IO uint32_t SR;
366  __IO uint32_t CR;
367  __IO uint32_t OPTCR;
368  __IO uint32_t OPTCR1;
369 } FLASH_TypeDef;
370 
371 
372 
377 typedef struct
378 {
379  __IO uint32_t BTCR[8];
380 } FSMC_Bank1_TypeDef;
381 
386 typedef struct
387 {
388  __IO uint32_t BWTR[7];
389 } FSMC_Bank1E_TypeDef;
390 
395 typedef struct
396 {
397  __IO uint32_t PCR2;
398  __IO uint32_t SR2;
399  __IO uint32_t PMEM2;
400  __IO uint32_t PATT2;
401  uint32_t RESERVED0;
402  __IO uint32_t ECCR2;
403  uint32_t RESERVED1;
404  uint32_t RESERVED2;
405  __IO uint32_t PCR3;
406  __IO uint32_t SR3;
407  __IO uint32_t PMEM3;
408  __IO uint32_t PATT3;
409  uint32_t RESERVED3;
410  __IO uint32_t ECCR3;
411 } FSMC_Bank2_3_TypeDef;
412 
417 typedef struct
418 {
419  __IO uint32_t PCR4;
420  __IO uint32_t SR4;
421  __IO uint32_t PMEM4;
422  __IO uint32_t PATT4;
423  __IO uint32_t PIO4;
424 } FSMC_Bank4_TypeDef;
425 
430 typedef struct
431 {
432  __IO uint32_t MODER;
433  __IO uint32_t OTYPER;
434  __IO uint32_t OSPEEDR;
435  __IO uint32_t PUPDR;
436  __IO uint32_t IDR;
437  __IO uint32_t ODR;
438  __IO uint32_t BSRR;
439  __IO uint32_t LCKR;
440  __IO uint32_t AFR[2];
441 } GPIO_TypeDef;
442 
447 typedef struct
448 {
449  __IO uint32_t MEMRMP;
450  __IO uint32_t PMC;
451  __IO uint32_t EXTICR[4];
452  uint32_t RESERVED[2];
453  __IO uint32_t CMPCR;
454 } SYSCFG_TypeDef;
455 
460 typedef struct
461 {
462  __IO uint32_t CR1;
463  __IO uint32_t CR2;
464  __IO uint32_t OAR1;
465  __IO uint32_t OAR2;
466  __IO uint32_t DR;
467  __IO uint32_t SR1;
468  __IO uint32_t SR2;
469  __IO uint32_t CCR;
470  __IO uint32_t TRISE;
471 } I2C_TypeDef;
472 
477 typedef struct
478 {
479  __IO uint32_t KR;
480  __IO uint32_t PR;
481  __IO uint32_t RLR;
482  __IO uint32_t SR;
483 } IWDG_TypeDef;
484 
485 
490 typedef struct
491 {
492  __IO uint32_t CR;
493  __IO uint32_t CSR;
494 } PWR_TypeDef;
495 
500 typedef struct
501 {
502  __IO uint32_t CR;
503  __IO uint32_t PLLCFGR;
504  __IO uint32_t CFGR;
505  __IO uint32_t CIR;
506  __IO uint32_t AHB1RSTR;
507  __IO uint32_t AHB2RSTR;
508  __IO uint32_t AHB3RSTR;
509  uint32_t RESERVED0;
510  __IO uint32_t APB1RSTR;
511  __IO uint32_t APB2RSTR;
512  uint32_t RESERVED1[2];
513  __IO uint32_t AHB1ENR;
514  __IO uint32_t AHB2ENR;
515  __IO uint32_t AHB3ENR;
516  uint32_t RESERVED2;
517  __IO uint32_t APB1ENR;
518  __IO uint32_t APB2ENR;
519  uint32_t RESERVED3[2];
520  __IO uint32_t AHB1LPENR;
521  __IO uint32_t AHB2LPENR;
522  __IO uint32_t AHB3LPENR;
523  uint32_t RESERVED4;
524  __IO uint32_t APB1LPENR;
525  __IO uint32_t APB2LPENR;
526  uint32_t RESERVED5[2];
527  __IO uint32_t BDCR;
528  __IO uint32_t CSR;
529  uint32_t RESERVED6[2];
530  __IO uint32_t SSCGR;
531  __IO uint32_t PLLI2SCFGR;
532 } RCC_TypeDef;
533 
538 typedef struct
539 {
540  __IO uint32_t TR;
541  __IO uint32_t DR;
542  __IO uint32_t CR;
543  __IO uint32_t ISR;
544  __IO uint32_t PRER;
545  __IO uint32_t WUTR;
546  __IO uint32_t CALIBR;
547  __IO uint32_t ALRMAR;
548  __IO uint32_t ALRMBR;
549  __IO uint32_t WPR;
550  __IO uint32_t SSR;
551  __IO uint32_t SHIFTR;
552  __IO uint32_t TSTR;
553  __IO uint32_t TSDR;
554  __IO uint32_t TSSSR;
555  __IO uint32_t CALR;
556  __IO uint32_t TAFCR;
557  __IO uint32_t ALRMASSR;
558  __IO uint32_t ALRMBSSR;
559  uint32_t RESERVED7;
560  __IO uint32_t BKP0R;
561  __IO uint32_t BKP1R;
562  __IO uint32_t BKP2R;
563  __IO uint32_t BKP3R;
564  __IO uint32_t BKP4R;
565  __IO uint32_t BKP5R;
566  __IO uint32_t BKP6R;
567  __IO uint32_t BKP7R;
568  __IO uint32_t BKP8R;
569  __IO uint32_t BKP9R;
570  __IO uint32_t BKP10R;
571  __IO uint32_t BKP11R;
572  __IO uint32_t BKP12R;
573  __IO uint32_t BKP13R;
574  __IO uint32_t BKP14R;
575  __IO uint32_t BKP15R;
576  __IO uint32_t BKP16R;
577  __IO uint32_t BKP17R;
578  __IO uint32_t BKP18R;
579  __IO uint32_t BKP19R;
580 } RTC_TypeDef;
581 
586 typedef struct
587 {
588  __IO uint32_t POWER;
589  __IO uint32_t CLKCR;
590  __IO uint32_t ARG;
591  __IO uint32_t CMD;
592  __IO const uint32_t RESPCMD;
593  __IO const uint32_t RESP1;
594  __IO const uint32_t RESP2;
595  __IO const uint32_t RESP3;
596  __IO const uint32_t RESP4;
597  __IO uint32_t DTIMER;
598  __IO uint32_t DLEN;
599  __IO uint32_t DCTRL;
600  __IO const uint32_t DCOUNT;
601  __IO const uint32_t STA;
602  __IO uint32_t ICR;
603  __IO uint32_t MASK;
604  uint32_t RESERVED0[2];
605  __IO const uint32_t FIFOCNT;
606  uint32_t RESERVED1[13];
607  __IO uint32_t FIFO;
608 } SDIO_TypeDef;
609 
614 typedef struct
615 {
616  __IO uint32_t CR1;
617  __IO uint32_t CR2;
618  __IO uint32_t SR;
619  __IO uint32_t DR;
620  __IO uint32_t CRCPR;
621  __IO uint32_t RXCRCR;
622  __IO uint32_t TXCRCR;
623  __IO uint32_t I2SCFGR;
624  __IO uint32_t I2SPR;
625 } SPI_TypeDef;
626 
627 
632 typedef struct
633 {
634  __IO uint32_t CR1;
635  __IO uint32_t CR2;
636  __IO uint32_t SMCR;
637  __IO uint32_t DIER;
638  __IO uint32_t SR;
639  __IO uint32_t EGR;
640  __IO uint32_t CCMR1;
641  __IO uint32_t CCMR2;
642  __IO uint32_t CCER;
643  __IO uint32_t CNT;
644  __IO uint32_t PSC;
645  __IO uint32_t ARR;
646  __IO uint32_t RCR;
647  __IO uint32_t CCR1;
648  __IO uint32_t CCR2;
649  __IO uint32_t CCR3;
650  __IO uint32_t CCR4;
651  __IO uint32_t BDTR;
652  __IO uint32_t DCR;
653  __IO uint32_t DMAR;
654  __IO uint32_t OR;
655 } TIM_TypeDef;
656 
661 typedef struct
662 {
663  __IO uint32_t SR;
664  __IO uint32_t DR;
665  __IO uint32_t BRR;
666  __IO uint32_t CR1;
667  __IO uint32_t CR2;
668  __IO uint32_t CR3;
669  __IO uint32_t GTPR;
670 } USART_TypeDef;
671 
676 typedef struct
677 {
678  __IO uint32_t CR;
679  __IO uint32_t CFR;
680  __IO uint32_t SR;
681 } WWDG_TypeDef;
682 
687 typedef struct
688 {
689  __IO uint32_t CR;
690  __IO uint32_t SR;
691  __IO uint32_t DR;
692 } RNG_TypeDef;
693 
697 typedef struct
698 {
699  __IO uint32_t GOTGCTL;
700  __IO uint32_t GOTGINT;
701  __IO uint32_t GAHBCFG;
702  __IO uint32_t GUSBCFG;
703  __IO uint32_t GRSTCTL;
704  __IO uint32_t GINTSTS;
705  __IO uint32_t GINTMSK;
706  __IO uint32_t GRXSTSR;
707  __IO uint32_t GRXSTSP;
708  __IO uint32_t GRXFSIZ;
709  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
710  __IO uint32_t HNPTXSTS;
711  uint32_t Reserved30[2];
712  __IO uint32_t GCCFG;
713  __IO uint32_t CID;
714  uint32_t Reserved40[48];
715  __IO uint32_t HPTXFSIZ;
716  __IO uint32_t DIEPTXF[0x0F];
717 } USB_OTG_GlobalTypeDef;
718 
722 typedef struct
723 {
724  __IO uint32_t DCFG;
725  __IO uint32_t DCTL;
726  __IO uint32_t DSTS;
727  uint32_t Reserved0C;
728  __IO uint32_t DIEPMSK;
729  __IO uint32_t DOEPMSK;
730  __IO uint32_t DAINT;
731  __IO uint32_t DAINTMSK;
732  uint32_t Reserved20;
733  uint32_t Reserved9;
734  __IO uint32_t DVBUSDIS;
735  __IO uint32_t DVBUSPULSE;
736  __IO uint32_t DTHRCTL;
737  __IO uint32_t DIEPEMPMSK;
738  __IO uint32_t DEACHINT;
739  __IO uint32_t DEACHMSK;
740  uint32_t Reserved40;
741  __IO uint32_t DINEP1MSK;
742  uint32_t Reserved44[15];
743  __IO uint32_t DOUTEP1MSK;
744 } USB_OTG_DeviceTypeDef;
745 
749 typedef struct
750 {
751  __IO uint32_t DIEPCTL;
752  uint32_t Reserved04;
753  __IO uint32_t DIEPINT;
754  uint32_t Reserved0C;
755  __IO uint32_t DIEPTSIZ;
756  __IO uint32_t DIEPDMA;
757  __IO uint32_t DTXFSTS;
758  uint32_t Reserved18;
759 } USB_OTG_INEndpointTypeDef;
760 
764 typedef struct
765 {
766  __IO uint32_t DOEPCTL;
767  uint32_t Reserved04;
768  __IO uint32_t DOEPINT;
769  uint32_t Reserved0C;
770  __IO uint32_t DOEPTSIZ;
771  __IO uint32_t DOEPDMA;
772  uint32_t Reserved18[2];
773 } USB_OTG_OUTEndpointTypeDef;
774 
778 typedef struct
779 {
780  __IO uint32_t HCFG;
781  __IO uint32_t HFIR;
782  __IO uint32_t HFNUM;
783  uint32_t Reserved40C;
784  __IO uint32_t HPTXSTS;
785  __IO uint32_t HAINT;
786  __IO uint32_t HAINTMSK;
787 } USB_OTG_HostTypeDef;
788 
792 typedef struct
793 {
794  __IO uint32_t HCCHAR;
795  __IO uint32_t HCSPLT;
796  __IO uint32_t HCINT;
797  __IO uint32_t HCINTMSK;
798  __IO uint32_t HCTSIZ;
799  __IO uint32_t HCDMA;
800  uint32_t Reserved[2];
801 } USB_OTG_HostChannelTypeDef;
802 
810 #define FLASH_BASE 0x08000000UL
811 #define CCMDATARAM_BASE 0x10000000UL
812 #define SRAM1_BASE 0x20000000UL
813 #define SRAM2_BASE 0x2001C000UL
814 #define PERIPH_BASE 0x40000000UL
815 #define BKPSRAM_BASE 0x40024000UL
816 #define FSMC_R_BASE 0xA0000000UL
817 #define SRAM1_BB_BASE 0x22000000UL
818 #define SRAM2_BB_BASE 0x22380000UL
819 #define PERIPH_BB_BASE 0x42000000UL
820 #define BKPSRAM_BB_BASE 0x42480000UL
821 #define FLASH_END 0x080FFFFFUL
822 #define FLASH_OTP_BASE 0x1FFF7800UL
823 #define FLASH_OTP_END 0x1FFF7A0FUL
824 #define CCMDATARAM_END 0x1000FFFFUL
826 /* Legacy defines */
827 #define SRAM_BASE SRAM1_BASE
828 #define SRAM_BB_BASE SRAM1_BB_BASE
829 
831 #define APB1PERIPH_BASE PERIPH_BASE
832 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
833 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
834 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
835 
837 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
838 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
839 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
840 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
841 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
842 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
843 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
844 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
845 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
846 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
847 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
848 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
849 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
850 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
851 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
852 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
853 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
854 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
855 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
856 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
857 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
858 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
859 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
860 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
861 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
862 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
863 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
864 
866 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
867 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
868 #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
869 #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
870 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
871 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
872 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
873 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
874 /* Legacy define */
875 #define ADC_BASE ADC123_COMMON_BASE
876 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
877 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
878 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
879 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
880 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
881 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
882 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
883 
885 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
886 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
887 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
888 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
889 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
890 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
891 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
892 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
893 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
894 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
895 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
896 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
897 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
898 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
899 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
900 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
901 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
902 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
903 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
904 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
905 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
906 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
907 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
908 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
909 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
910 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
911 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
912 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
913 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
914 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
915 
917 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
918 
920 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
921 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
922 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)
923 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
924 
925 
927 #define DBGMCU_BASE 0xE0042000UL
929 #define USB_OTG_HS_PERIPH_BASE 0x40040000UL
930 #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
931 
932 #define USB_OTG_GLOBAL_BASE 0x000UL
933 #define USB_OTG_DEVICE_BASE 0x800UL
934 #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
935 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
936 #define USB_OTG_EP_REG_SIZE 0x20UL
937 #define USB_OTG_HOST_BASE 0x400UL
938 #define USB_OTG_HOST_PORT_BASE 0x440UL
939 #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
940 #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
941 #define USB_OTG_PCGCCTL_BASE 0xE00UL
942 #define USB_OTG_FIFO_BASE 0x1000UL
943 #define USB_OTG_FIFO_SIZE 0x1000UL
944 
945 #define UID_BASE 0x1FFF7A10UL
946 #define FLASHSIZE_BASE 0x1FFF7A22UL
947 #define PACKAGE_BASE 0x1FFF7BF0UL
955 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
956 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
957 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
958 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
959 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
960 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
961 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
962 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
963 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
964 #define RTC ((RTC_TypeDef *) RTC_BASE)
965 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
966 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
967 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
968 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
969 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
970 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
971 #define USART2 ((USART_TypeDef *) USART2_BASE)
972 #define USART3 ((USART_TypeDef *) USART3_BASE)
973 #define UART4 ((USART_TypeDef *) UART4_BASE)
974 #define UART5 ((USART_TypeDef *) UART5_BASE)
975 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
976 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
977 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
978 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
979 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
980 #define PWR ((PWR_TypeDef *) PWR_BASE)
981 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
982 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
983 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
984 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
985 #define USART1 ((USART_TypeDef *) USART1_BASE)
986 #define USART6 ((USART_TypeDef *) USART6_BASE)
987 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
988 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
989 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
990 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
991 /* Legacy define */
992 #define ADC ADC123_COMMON
993 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
994 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
995 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
996 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
997 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
998 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
999 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1000 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1001 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1002 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1003 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1004 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1005 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1006 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1007 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1008 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1009 #define CRC ((CRC_TypeDef *) CRC_BASE)
1010 #define RCC ((RCC_TypeDef *) RCC_BASE)
1011 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1012 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1013 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1014 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1015 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1016 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1017 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1018 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1019 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1020 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1021 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1022 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1023 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1024 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1025 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1026 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1027 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1028 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1029 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1030 #define RNG ((RNG_TypeDef *) RNG_BASE)
1031 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1032 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1033 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1034 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1035 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1036 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1037 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1038 
1050 #define LSI_STARTUP_TIME 40U
1059 /******************************************************************************/
1060 /* Peripheral Registers_Bits_Definition */
1061 /******************************************************************************/
1062 
1063 /******************************************************************************/
1064 /* */
1065 /* Analog to Digital Converter */
1066 /* */
1067 /******************************************************************************/
1068 /*
1069  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1070  */
1071 #define ADC_MULTIMODE_SUPPORT
1073 /******************** Bit definition for ADC_SR register ********************/
1074 #define ADC_SR_AWD_Pos (0U)
1075 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1076 #define ADC_SR_AWD ADC_SR_AWD_Msk
1077 #define ADC_SR_EOC_Pos (1U)
1078 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1079 #define ADC_SR_EOC ADC_SR_EOC_Msk
1080 #define ADC_SR_JEOC_Pos (2U)
1081 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1082 #define ADC_SR_JEOC ADC_SR_JEOC_Msk
1083 #define ADC_SR_JSTRT_Pos (3U)
1084 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1085 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1086 #define ADC_SR_STRT_Pos (4U)
1087 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1088 #define ADC_SR_STRT ADC_SR_STRT_Msk
1089 #define ADC_SR_OVR_Pos (5U)
1090 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1091 #define ADC_SR_OVR ADC_SR_OVR_Msk
1093 /******************* Bit definition for ADC_CR1 register ********************/
1094 #define ADC_CR1_AWDCH_Pos (0U)
1095 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1096 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1097 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1098 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1099 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1100 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1101 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1102 #define ADC_CR1_EOCIE_Pos (5U)
1103 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1104 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1105 #define ADC_CR1_AWDIE_Pos (6U)
1106 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1107 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1108 #define ADC_CR1_JEOCIE_Pos (7U)
1109 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1110 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1111 #define ADC_CR1_SCAN_Pos (8U)
1112 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1113 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1114 #define ADC_CR1_AWDSGL_Pos (9U)
1115 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1116 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1117 #define ADC_CR1_JAUTO_Pos (10U)
1118 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1119 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1120 #define ADC_CR1_DISCEN_Pos (11U)
1121 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1122 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1123 #define ADC_CR1_JDISCEN_Pos (12U)
1124 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1125 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1126 #define ADC_CR1_DISCNUM_Pos (13U)
1127 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1128 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1129 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1130 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1131 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1132 #define ADC_CR1_JAWDEN_Pos (22U)
1133 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1134 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1135 #define ADC_CR1_AWDEN_Pos (23U)
1136 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1137 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1138 #define ADC_CR1_RES_Pos (24U)
1139 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1140 #define ADC_CR1_RES ADC_CR1_RES_Msk
1141 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1142 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1143 #define ADC_CR1_OVRIE_Pos (26U)
1144 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1145 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1147 /******************* Bit definition for ADC_CR2 register ********************/
1148 #define ADC_CR2_ADON_Pos (0U)
1149 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1150 #define ADC_CR2_ADON ADC_CR2_ADON_Msk
1151 #define ADC_CR2_CONT_Pos (1U)
1152 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1153 #define ADC_CR2_CONT ADC_CR2_CONT_Msk
1154 #define ADC_CR2_DMA_Pos (8U)
1155 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1156 #define ADC_CR2_DMA ADC_CR2_DMA_Msk
1157 #define ADC_CR2_DDS_Pos (9U)
1158 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1159 #define ADC_CR2_DDS ADC_CR2_DDS_Msk
1160 #define ADC_CR2_EOCS_Pos (10U)
1161 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1162 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1163 #define ADC_CR2_ALIGN_Pos (11U)
1164 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1165 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1166 #define ADC_CR2_JEXTSEL_Pos (16U)
1167 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1168 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1169 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1170 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1171 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1172 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1173 #define ADC_CR2_JEXTEN_Pos (20U)
1174 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1175 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1176 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1177 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1178 #define ADC_CR2_JSWSTART_Pos (22U)
1179 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1180 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1181 #define ADC_CR2_EXTSEL_Pos (24U)
1182 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1183 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1184 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1185 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1186 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1187 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1188 #define ADC_CR2_EXTEN_Pos (28U)
1189 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1190 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1191 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1192 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1193 #define ADC_CR2_SWSTART_Pos (30U)
1194 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1195 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1197 /****************** Bit definition for ADC_SMPR1 register *******************/
1198 #define ADC_SMPR1_SMP10_Pos (0U)
1199 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1200 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1201 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1202 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1203 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1204 #define ADC_SMPR1_SMP11_Pos (3U)
1205 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1206 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1207 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1208 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1209 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1210 #define ADC_SMPR1_SMP12_Pos (6U)
1211 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1212 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1213 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1214 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1215 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1216 #define ADC_SMPR1_SMP13_Pos (9U)
1217 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1218 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1219 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1220 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1221 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1222 #define ADC_SMPR1_SMP14_Pos (12U)
1223 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1224 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1225 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1226 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1227 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1228 #define ADC_SMPR1_SMP15_Pos (15U)
1229 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1230 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1231 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1232 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1233 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1234 #define ADC_SMPR1_SMP16_Pos (18U)
1235 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1236 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1237 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1238 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1239 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1240 #define ADC_SMPR1_SMP17_Pos (21U)
1241 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1242 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1243 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1244 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1245 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1246 #define ADC_SMPR1_SMP18_Pos (24U)
1247 #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1248 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1249 #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1250 #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1251 #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1253 /****************** Bit definition for ADC_SMPR2 register *******************/
1254 #define ADC_SMPR2_SMP0_Pos (0U)
1255 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1256 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1257 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1258 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1259 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1260 #define ADC_SMPR2_SMP1_Pos (3U)
1261 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1262 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1263 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1264 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1265 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1266 #define ADC_SMPR2_SMP2_Pos (6U)
1267 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1268 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1269 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1270 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1271 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1272 #define ADC_SMPR2_SMP3_Pos (9U)
1273 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1274 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1275 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1276 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1277 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1278 #define ADC_SMPR2_SMP4_Pos (12U)
1279 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1280 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1281 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1282 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1283 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1284 #define ADC_SMPR2_SMP5_Pos (15U)
1285 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1286 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1287 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1288 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1289 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1290 #define ADC_SMPR2_SMP6_Pos (18U)
1291 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1292 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1293 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1294 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1295 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1296 #define ADC_SMPR2_SMP7_Pos (21U)
1297 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1298 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1299 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1300 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1301 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1302 #define ADC_SMPR2_SMP8_Pos (24U)
1303 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1304 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1305 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1306 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1307 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1308 #define ADC_SMPR2_SMP9_Pos (27U)
1309 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1310 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1311 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1312 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1313 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1315 /****************** Bit definition for ADC_JOFR1 register *******************/
1316 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1317 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1318 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1320 /****************** Bit definition for ADC_JOFR2 register *******************/
1321 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1322 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1323 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1325 /****************** Bit definition for ADC_JOFR3 register *******************/
1326 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1327 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1328 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1330 /****************** Bit definition for ADC_JOFR4 register *******************/
1331 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1332 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1333 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1335 /******************* Bit definition for ADC_HTR register ********************/
1336 #define ADC_HTR_HT_Pos (0U)
1337 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1338 #define ADC_HTR_HT ADC_HTR_HT_Msk
1340 /******************* Bit definition for ADC_LTR register ********************/
1341 #define ADC_LTR_LT_Pos (0U)
1342 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1343 #define ADC_LTR_LT ADC_LTR_LT_Msk
1345 /******************* Bit definition for ADC_SQR1 register *******************/
1346 #define ADC_SQR1_SQ13_Pos (0U)
1347 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1348 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1349 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1350 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1351 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1352 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1353 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1354 #define ADC_SQR1_SQ14_Pos (5U)
1355 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1356 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1357 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1358 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1359 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1360 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1361 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1362 #define ADC_SQR1_SQ15_Pos (10U)
1363 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1364 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1365 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1366 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1367 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1368 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1369 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1370 #define ADC_SQR1_SQ16_Pos (15U)
1371 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1372 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1373 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1374 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1375 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1376 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1377 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1378 #define ADC_SQR1_L_Pos (20U)
1379 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1380 #define ADC_SQR1_L ADC_SQR1_L_Msk
1381 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1382 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1383 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1384 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1386 /******************* Bit definition for ADC_SQR2 register *******************/
1387 #define ADC_SQR2_SQ7_Pos (0U)
1388 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1389 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1390 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1391 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1392 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1393 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1394 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1395 #define ADC_SQR2_SQ8_Pos (5U)
1396 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1397 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1398 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1399 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1400 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1401 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1402 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1403 #define ADC_SQR2_SQ9_Pos (10U)
1404 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1405 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1406 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1407 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1408 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1409 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1410 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1411 #define ADC_SQR2_SQ10_Pos (15U)
1412 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1413 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1414 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1415 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1416 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1417 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1418 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1419 #define ADC_SQR2_SQ11_Pos (20U)
1420 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1421 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1422 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1423 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1424 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1425 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1426 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1427 #define ADC_SQR2_SQ12_Pos (25U)
1428 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1429 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1430 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1431 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1432 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1433 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1434 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1436 /******************* Bit definition for ADC_SQR3 register *******************/
1437 #define ADC_SQR3_SQ1_Pos (0U)
1438 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1439 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1440 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1441 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1442 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1443 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1444 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1445 #define ADC_SQR3_SQ2_Pos (5U)
1446 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1447 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1448 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1449 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1450 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1451 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1452 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1453 #define ADC_SQR3_SQ3_Pos (10U)
1454 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1455 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1456 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1457 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1458 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1459 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1460 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1461 #define ADC_SQR3_SQ4_Pos (15U)
1462 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1463 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1464 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1465 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1466 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1467 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1468 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1469 #define ADC_SQR3_SQ5_Pos (20U)
1470 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1471 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1472 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1473 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1474 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1475 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1476 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1477 #define ADC_SQR3_SQ6_Pos (25U)
1478 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1479 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1480 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1481 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1482 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1483 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1484 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1486 /******************* Bit definition for ADC_JSQR register *******************/
1487 #define ADC_JSQR_JSQ1_Pos (0U)
1488 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1489 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1490 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1491 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1492 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1493 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1494 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1495 #define ADC_JSQR_JSQ2_Pos (5U)
1496 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1497 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1498 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1499 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1500 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1501 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1502 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1503 #define ADC_JSQR_JSQ3_Pos (10U)
1504 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1505 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1506 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1507 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1508 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1509 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1510 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1511 #define ADC_JSQR_JSQ4_Pos (15U)
1512 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1513 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1514 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1515 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1516 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1517 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1518 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1519 #define ADC_JSQR_JL_Pos (20U)
1520 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1521 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
1522 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1523 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1525 /******************* Bit definition for ADC_JDR1 register *******************/
1526 #define ADC_JDR1_JDATA_Pos (0U)
1527 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1528 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1530 /******************* Bit definition for ADC_JDR2 register *******************/
1531 #define ADC_JDR2_JDATA_Pos (0U)
1532 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1533 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1535 /******************* Bit definition for ADC_JDR3 register *******************/
1536 #define ADC_JDR3_JDATA_Pos (0U)
1537 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1538 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1540 /******************* Bit definition for ADC_JDR4 register *******************/
1541 #define ADC_JDR4_JDATA_Pos (0U)
1542 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1543 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1545 /******************** Bit definition for ADC_DR register ********************/
1546 #define ADC_DR_DATA_Pos (0U)
1547 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1548 #define ADC_DR_DATA ADC_DR_DATA_Msk
1549 #define ADC_DR_ADC2DATA_Pos (16U)
1550 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1551 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1553 /******************* Bit definition for ADC_CSR register ********************/
1554 #define ADC_CSR_AWD1_Pos (0U)
1555 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1556 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1557 #define ADC_CSR_EOC1_Pos (1U)
1558 #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1559 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1560 #define ADC_CSR_JEOC1_Pos (2U)
1561 #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1562 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1563 #define ADC_CSR_JSTRT1_Pos (3U)
1564 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1565 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1566 #define ADC_CSR_STRT1_Pos (4U)
1567 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1568 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1569 #define ADC_CSR_OVR1_Pos (5U)
1570 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1571 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1572 #define ADC_CSR_AWD2_Pos (8U)
1573 #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1574 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1575 #define ADC_CSR_EOC2_Pos (9U)
1576 #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1577 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1578 #define ADC_CSR_JEOC2_Pos (10U)
1579 #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1580 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1581 #define ADC_CSR_JSTRT2_Pos (11U)
1582 #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1583 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1584 #define ADC_CSR_STRT2_Pos (12U)
1585 #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1586 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1587 #define ADC_CSR_OVR2_Pos (13U)
1588 #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1589 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1590 #define ADC_CSR_AWD3_Pos (16U)
1591 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1592 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1593 #define ADC_CSR_EOC3_Pos (17U)
1594 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1595 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1596 #define ADC_CSR_JEOC3_Pos (18U)
1597 #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1598 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1599 #define ADC_CSR_JSTRT3_Pos (19U)
1600 #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1601 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1602 #define ADC_CSR_STRT3_Pos (20U)
1603 #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1604 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1605 #define ADC_CSR_OVR3_Pos (21U)
1606 #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1607 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1609 /* Legacy defines */
1610 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1611 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1612 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1613 
1614 /******************* Bit definition for ADC_CCR register ********************/
1615 #define ADC_CCR_MULTI_Pos (0U)
1616 #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1617 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1618 #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1619 #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1620 #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1621 #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1622 #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1623 #define ADC_CCR_DELAY_Pos (8U)
1624 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1625 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1626 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1627 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1628 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1629 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1630 #define ADC_CCR_DDS_Pos (13U)
1631 #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1632 #define ADC_CCR_DDS ADC_CCR_DDS_Msk
1633 #define ADC_CCR_DMA_Pos (14U)
1634 #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1635 #define ADC_CCR_DMA ADC_CCR_DMA_Msk
1636 #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1637 #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1638 #define ADC_CCR_ADCPRE_Pos (16U)
1639 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1640 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1641 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1642 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1643 #define ADC_CCR_VBATE_Pos (22U)
1644 #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1645 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1646 #define ADC_CCR_TSVREFE_Pos (23U)
1647 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1648 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1650 /******************* Bit definition for ADC_CDR register ********************/
1651 #define ADC_CDR_DATA1_Pos (0U)
1652 #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1653 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1654 #define ADC_CDR_DATA2_Pos (16U)
1655 #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1656 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1658 /* Legacy defines */
1659 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1660 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1661 
1662 /******************************************************************************/
1663 /* */
1664 /* Controller Area Network */
1665 /* */
1666 /******************************************************************************/
1668 /******************* Bit definition for CAN_MCR register ********************/
1669 #define CAN_MCR_INRQ_Pos (0U)
1670 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1671 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1672 #define CAN_MCR_SLEEP_Pos (1U)
1673 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1674 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1675 #define CAN_MCR_TXFP_Pos (2U)
1676 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1677 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1678 #define CAN_MCR_RFLM_Pos (3U)
1679 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1680 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1681 #define CAN_MCR_NART_Pos (4U)
1682 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1683 #define CAN_MCR_NART CAN_MCR_NART_Msk
1684 #define CAN_MCR_AWUM_Pos (5U)
1685 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1686 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1687 #define CAN_MCR_ABOM_Pos (6U)
1688 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1689 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1690 #define CAN_MCR_TTCM_Pos (7U)
1691 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1692 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1693 #define CAN_MCR_RESET_Pos (15U)
1694 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1695 #define CAN_MCR_RESET CAN_MCR_RESET_Msk
1696 #define CAN_MCR_DBF_Pos (16U)
1697 #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1698 #define CAN_MCR_DBF CAN_MCR_DBF_Msk
1699 /******************* Bit definition for CAN_MSR register ********************/
1700 #define CAN_MSR_INAK_Pos (0U)
1701 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1702 #define CAN_MSR_INAK CAN_MSR_INAK_Msk
1703 #define CAN_MSR_SLAK_Pos (1U)
1704 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1705 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1706 #define CAN_MSR_ERRI_Pos (2U)
1707 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1708 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1709 #define CAN_MSR_WKUI_Pos (3U)
1710 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1711 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1712 #define CAN_MSR_SLAKI_Pos (4U)
1713 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1714 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1715 #define CAN_MSR_TXM_Pos (8U)
1716 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1717 #define CAN_MSR_TXM CAN_MSR_TXM_Msk
1718 #define CAN_MSR_RXM_Pos (9U)
1719 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1720 #define CAN_MSR_RXM CAN_MSR_RXM_Msk
1721 #define CAN_MSR_SAMP_Pos (10U)
1722 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1723 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1724 #define CAN_MSR_RX_Pos (11U)
1725 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1726 #define CAN_MSR_RX CAN_MSR_RX_Msk
1728 /******************* Bit definition for CAN_TSR register ********************/
1729 #define CAN_TSR_RQCP0_Pos (0U)
1730 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1731 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1732 #define CAN_TSR_TXOK0_Pos (1U)
1733 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1734 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1735 #define CAN_TSR_ALST0_Pos (2U)
1736 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1737 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1738 #define CAN_TSR_TERR0_Pos (3U)
1739 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1740 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1741 #define CAN_TSR_ABRQ0_Pos (7U)
1742 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1743 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1744 #define CAN_TSR_RQCP1_Pos (8U)
1745 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1746 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1747 #define CAN_TSR_TXOK1_Pos (9U)
1748 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1749 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1750 #define CAN_TSR_ALST1_Pos (10U)
1751 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1752 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1753 #define CAN_TSR_TERR1_Pos (11U)
1754 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1755 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1756 #define CAN_TSR_ABRQ1_Pos (15U)
1757 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1758 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1759 #define CAN_TSR_RQCP2_Pos (16U)
1760 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1761 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1762 #define CAN_TSR_TXOK2_Pos (17U)
1763 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1764 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1765 #define CAN_TSR_ALST2_Pos (18U)
1766 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1767 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1768 #define CAN_TSR_TERR2_Pos (19U)
1769 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1770 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1771 #define CAN_TSR_ABRQ2_Pos (23U)
1772 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1773 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1774 #define CAN_TSR_CODE_Pos (24U)
1775 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1776 #define CAN_TSR_CODE CAN_TSR_CODE_Msk
1778 #define CAN_TSR_TME_Pos (26U)
1779 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1780 #define CAN_TSR_TME CAN_TSR_TME_Msk
1781 #define CAN_TSR_TME0_Pos (26U)
1782 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1783 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1784 #define CAN_TSR_TME1_Pos (27U)
1785 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1786 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1787 #define CAN_TSR_TME2_Pos (28U)
1788 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1789 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1791 #define CAN_TSR_LOW_Pos (29U)
1792 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1793 #define CAN_TSR_LOW CAN_TSR_LOW_Msk
1794 #define CAN_TSR_LOW0_Pos (29U)
1795 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1796 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1797 #define CAN_TSR_LOW1_Pos (30U)
1798 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1799 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1800 #define CAN_TSR_LOW2_Pos (31U)
1801 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1802 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1804 /******************* Bit definition for CAN_RF0R register *******************/
1805 #define CAN_RF0R_FMP0_Pos (0U)
1806 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1807 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1808 #define CAN_RF0R_FULL0_Pos (3U)
1809 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1810 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1811 #define CAN_RF0R_FOVR0_Pos (4U)
1812 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1813 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1814 #define CAN_RF0R_RFOM0_Pos (5U)
1815 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1816 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1818 /******************* Bit definition for CAN_RF1R register *******************/
1819 #define CAN_RF1R_FMP1_Pos (0U)
1820 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1821 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1822 #define CAN_RF1R_FULL1_Pos (3U)
1823 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1824 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1825 #define CAN_RF1R_FOVR1_Pos (4U)
1826 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1827 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1828 #define CAN_RF1R_RFOM1_Pos (5U)
1829 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1830 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1832 /******************** Bit definition for CAN_IER register *******************/
1833 #define CAN_IER_TMEIE_Pos (0U)
1834 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1835 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1836 #define CAN_IER_FMPIE0_Pos (1U)
1837 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1838 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1839 #define CAN_IER_FFIE0_Pos (2U)
1840 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1841 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1842 #define CAN_IER_FOVIE0_Pos (3U)
1843 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1844 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1845 #define CAN_IER_FMPIE1_Pos (4U)
1846 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1847 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1848 #define CAN_IER_FFIE1_Pos (5U)
1849 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1850 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1851 #define CAN_IER_FOVIE1_Pos (6U)
1852 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1853 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1854 #define CAN_IER_EWGIE_Pos (8U)
1855 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1856 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1857 #define CAN_IER_EPVIE_Pos (9U)
1858 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1859 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1860 #define CAN_IER_BOFIE_Pos (10U)
1861 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1862 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1863 #define CAN_IER_LECIE_Pos (11U)
1864 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1865 #define CAN_IER_LECIE CAN_IER_LECIE_Msk
1866 #define CAN_IER_ERRIE_Pos (15U)
1867 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1868 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1869 #define CAN_IER_WKUIE_Pos (16U)
1870 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1871 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1872 #define CAN_IER_SLKIE_Pos (17U)
1873 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1874 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1875 #define CAN_IER_EWGIE_Pos (8U)
1876 
1877 /******************** Bit definition for CAN_ESR register *******************/
1878 #define CAN_ESR_EWGF_Pos (0U)
1879 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1880 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1881 #define CAN_ESR_EPVF_Pos (1U)
1882 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1883 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1884 #define CAN_ESR_BOFF_Pos (2U)
1885 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1886 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1888 #define CAN_ESR_LEC_Pos (4U)
1889 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
1890 #define CAN_ESR_LEC CAN_ESR_LEC_Msk
1891 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
1892 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
1893 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
1895 #define CAN_ESR_TEC_Pos (16U)
1896 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
1897 #define CAN_ESR_TEC CAN_ESR_TEC_Msk
1898 #define CAN_ESR_REC_Pos (24U)
1899 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
1900 #define CAN_ESR_REC CAN_ESR_REC_Msk
1902 /******************* Bit definition for CAN_BTR register ********************/
1903 #define CAN_BTR_BRP_Pos (0U)
1904 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
1905 #define CAN_BTR_BRP CAN_BTR_BRP_Msk
1906 #define CAN_BTR_TS1_Pos (16U)
1907 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
1908 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk
1909 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
1910 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
1911 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
1912 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
1913 #define CAN_BTR_TS2_Pos (20U)
1914 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
1915 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk
1916 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
1917 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
1918 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
1919 #define CAN_BTR_SJW_Pos (24U)
1920 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
1921 #define CAN_BTR_SJW CAN_BTR_SJW_Msk
1922 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
1923 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
1924 #define CAN_BTR_LBKM_Pos (30U)
1925 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
1926 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
1927 #define CAN_BTR_SILM_Pos (31U)
1928 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
1929 #define CAN_BTR_SILM CAN_BTR_SILM_Msk
1933 /****************** Bit definition for CAN_TI0R register ********************/
1934 #define CAN_TI0R_TXRQ_Pos (0U)
1935 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
1936 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
1937 #define CAN_TI0R_RTR_Pos (1U)
1938 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
1939 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
1940 #define CAN_TI0R_IDE_Pos (2U)
1941 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
1942 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
1943 #define CAN_TI0R_EXID_Pos (3U)
1944 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
1945 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
1946 #define CAN_TI0R_STID_Pos (21U)
1947 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
1948 #define CAN_TI0R_STID CAN_TI0R_STID_Msk
1950 /****************** Bit definition for CAN_TDT0R register *******************/
1951 #define CAN_TDT0R_DLC_Pos (0U)
1952 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
1953 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
1954 #define CAN_TDT0R_TGT_Pos (8U)
1955 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
1956 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
1957 #define CAN_TDT0R_TIME_Pos (16U)
1958 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
1959 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
1961 /****************** Bit definition for CAN_TDL0R register *******************/
1962 #define CAN_TDL0R_DATA0_Pos (0U)
1963 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
1964 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
1965 #define CAN_TDL0R_DATA1_Pos (8U)
1966 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
1967 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
1968 #define CAN_TDL0R_DATA2_Pos (16U)
1969 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
1970 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
1971 #define CAN_TDL0R_DATA3_Pos (24U)
1972 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
1973 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
1975 /****************** Bit definition for CAN_TDH0R register *******************/
1976 #define CAN_TDH0R_DATA4_Pos (0U)
1977 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
1978 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
1979 #define CAN_TDH0R_DATA5_Pos (8U)
1980 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
1981 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
1982 #define CAN_TDH0R_DATA6_Pos (16U)
1983 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
1984 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
1985 #define CAN_TDH0R_DATA7_Pos (24U)
1986 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
1987 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
1989 /******************* Bit definition for CAN_TI1R register *******************/
1990 #define CAN_TI1R_TXRQ_Pos (0U)
1991 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
1992 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
1993 #define CAN_TI1R_RTR_Pos (1U)
1994 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
1995 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
1996 #define CAN_TI1R_IDE_Pos (2U)
1997 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
1998 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
1999 #define CAN_TI1R_EXID_Pos (3U)
2000 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2001 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2002 #define CAN_TI1R_STID_Pos (21U)
2003 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2004 #define CAN_TI1R_STID CAN_TI1R_STID_Msk
2006 /******************* Bit definition for CAN_TDT1R register ******************/
2007 #define CAN_TDT1R_DLC_Pos (0U)
2008 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2009 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2010 #define CAN_TDT1R_TGT_Pos (8U)
2011 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2012 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2013 #define CAN_TDT1R_TIME_Pos (16U)
2014 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2015 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2017 /******************* Bit definition for CAN_TDL1R register ******************/
2018 #define CAN_TDL1R_DATA0_Pos (0U)
2019 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2020 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2021 #define CAN_TDL1R_DATA1_Pos (8U)
2022 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2023 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2024 #define CAN_TDL1R_DATA2_Pos (16U)
2025 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2026 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2027 #define CAN_TDL1R_DATA3_Pos (24U)
2028 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2029 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2031 /******************* Bit definition for CAN_TDH1R register ******************/
2032 #define CAN_TDH1R_DATA4_Pos (0U)
2033 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2034 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2035 #define CAN_TDH1R_DATA5_Pos (8U)
2036 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2037 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2038 #define CAN_TDH1R_DATA6_Pos (16U)
2039 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2040 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2041 #define CAN_TDH1R_DATA7_Pos (24U)
2042 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2043 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2045 /******************* Bit definition for CAN_TI2R register *******************/
2046 #define CAN_TI2R_TXRQ_Pos (0U)
2047 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2048 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2049 #define CAN_TI2R_RTR_Pos (1U)
2050 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2051 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2052 #define CAN_TI2R_IDE_Pos (2U)
2053 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2054 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2055 #define CAN_TI2R_EXID_Pos (3U)
2056 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2057 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2058 #define CAN_TI2R_STID_Pos (21U)
2059 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2060 #define CAN_TI2R_STID CAN_TI2R_STID_Msk
2062 /******************* Bit definition for CAN_TDT2R register ******************/
2063 #define CAN_TDT2R_DLC_Pos (0U)
2064 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2065 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2066 #define CAN_TDT2R_TGT_Pos (8U)
2067 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2068 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2069 #define CAN_TDT2R_TIME_Pos (16U)
2070 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2071 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2073 /******************* Bit definition for CAN_TDL2R register ******************/
2074 #define CAN_TDL2R_DATA0_Pos (0U)
2075 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2076 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2077 #define CAN_TDL2R_DATA1_Pos (8U)
2078 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2079 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2080 #define CAN_TDL2R_DATA2_Pos (16U)
2081 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2082 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2083 #define CAN_TDL2R_DATA3_Pos (24U)
2084 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2085 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2087 /******************* Bit definition for CAN_TDH2R register ******************/
2088 #define CAN_TDH2R_DATA4_Pos (0U)
2089 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2090 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2091 #define CAN_TDH2R_DATA5_Pos (8U)
2092 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2093 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2094 #define CAN_TDH2R_DATA6_Pos (16U)
2095 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2096 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2097 #define CAN_TDH2R_DATA7_Pos (24U)
2098 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2099 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2101 /******************* Bit definition for CAN_RI0R register *******************/
2102 #define CAN_RI0R_RTR_Pos (1U)
2103 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2104 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2105 #define CAN_RI0R_IDE_Pos (2U)
2106 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2107 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2108 #define CAN_RI0R_EXID_Pos (3U)
2109 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2110 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2111 #define CAN_RI0R_STID_Pos (21U)
2112 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2113 #define CAN_RI0R_STID CAN_RI0R_STID_Msk
2115 /******************* Bit definition for CAN_RDT0R register ******************/
2116 #define CAN_RDT0R_DLC_Pos (0U)
2117 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2118 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2119 #define CAN_RDT0R_FMI_Pos (8U)
2120 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2121 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2122 #define CAN_RDT0R_TIME_Pos (16U)
2123 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2124 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2126 /******************* Bit definition for CAN_RDL0R register ******************/
2127 #define CAN_RDL0R_DATA0_Pos (0U)
2128 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2129 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2130 #define CAN_RDL0R_DATA1_Pos (8U)
2131 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2132 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2133 #define CAN_RDL0R_DATA2_Pos (16U)
2134 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2135 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2136 #define CAN_RDL0R_DATA3_Pos (24U)
2137 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2138 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2140 /******************* Bit definition for CAN_RDH0R register ******************/
2141 #define CAN_RDH0R_DATA4_Pos (0U)
2142 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2143 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2144 #define CAN_RDH0R_DATA5_Pos (8U)
2145 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2146 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2147 #define CAN_RDH0R_DATA6_Pos (16U)
2148 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2149 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2150 #define CAN_RDH0R_DATA7_Pos (24U)
2151 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2152 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2154 /******************* Bit definition for CAN_RI1R register *******************/
2155 #define CAN_RI1R_RTR_Pos (1U)
2156 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2157 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2158 #define CAN_RI1R_IDE_Pos (2U)
2159 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2160 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2161 #define CAN_RI1R_EXID_Pos (3U)
2162 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2163 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2164 #define CAN_RI1R_STID_Pos (21U)
2165 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2166 #define CAN_RI1R_STID CAN_RI1R_STID_Msk
2168 /******************* Bit definition for CAN_RDT1R register ******************/
2169 #define CAN_RDT1R_DLC_Pos (0U)
2170 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2171 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2172 #define CAN_RDT1R_FMI_Pos (8U)
2173 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2174 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2175 #define CAN_RDT1R_TIME_Pos (16U)
2176 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2177 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2179 /******************* Bit definition for CAN_RDL1R register ******************/
2180 #define CAN_RDL1R_DATA0_Pos (0U)
2181 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2182 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2183 #define CAN_RDL1R_DATA1_Pos (8U)
2184 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2185 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2186 #define CAN_RDL1R_DATA2_Pos (16U)
2187 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2188 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2189 #define CAN_RDL1R_DATA3_Pos (24U)
2190 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2191 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2193 /******************* Bit definition for CAN_RDH1R register ******************/
2194 #define CAN_RDH1R_DATA4_Pos (0U)
2195 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2196 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2197 #define CAN_RDH1R_DATA5_Pos (8U)
2198 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2199 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2200 #define CAN_RDH1R_DATA6_Pos (16U)
2201 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2202 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2203 #define CAN_RDH1R_DATA7_Pos (24U)
2204 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2205 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2208 /******************* Bit definition for CAN_FMR register ********************/
2209 #define CAN_FMR_FINIT_Pos (0U)
2210 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2211 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2212 #define CAN_FMR_CAN2SB_Pos (8U)
2213 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2214 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2216 /******************* Bit definition for CAN_FM1R register *******************/
2217 #define CAN_FM1R_FBM_Pos (0U)
2218 #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2219 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2220 #define CAN_FM1R_FBM0_Pos (0U)
2221 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2222 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2223 #define CAN_FM1R_FBM1_Pos (1U)
2224 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2225 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2226 #define CAN_FM1R_FBM2_Pos (2U)
2227 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2228 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2229 #define CAN_FM1R_FBM3_Pos (3U)
2230 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2231 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2232 #define CAN_FM1R_FBM4_Pos (4U)
2233 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2234 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2235 #define CAN_FM1R_FBM5_Pos (5U)
2236 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2237 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2238 #define CAN_FM1R_FBM6_Pos (6U)
2239 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2240 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2241 #define CAN_FM1R_FBM7_Pos (7U)
2242 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2243 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2244 #define CAN_FM1R_FBM8_Pos (8U)
2245 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2246 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2247 #define CAN_FM1R_FBM9_Pos (9U)
2248 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2249 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2250 #define CAN_FM1R_FBM10_Pos (10U)
2251 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2252 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2253 #define CAN_FM1R_FBM11_Pos (11U)
2254 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2255 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2256 #define CAN_FM1R_FBM12_Pos (12U)
2257 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2258 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2259 #define CAN_FM1R_FBM13_Pos (13U)
2260 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2261 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2262 #define CAN_FM1R_FBM14_Pos (14U)
2263 #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2264 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2265 #define CAN_FM1R_FBM15_Pos (15U)
2266 #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2267 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2268 #define CAN_FM1R_FBM16_Pos (16U)
2269 #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2270 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2271 #define CAN_FM1R_FBM17_Pos (17U)
2272 #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2273 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2274 #define CAN_FM1R_FBM18_Pos (18U)
2275 #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2276 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2277 #define CAN_FM1R_FBM19_Pos (19U)
2278 #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2279 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2280 #define CAN_FM1R_FBM20_Pos (20U)
2281 #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2282 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2283 #define CAN_FM1R_FBM21_Pos (21U)
2284 #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2285 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2286 #define CAN_FM1R_FBM22_Pos (22U)
2287 #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2288 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2289 #define CAN_FM1R_FBM23_Pos (23U)
2290 #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2291 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2292 #define CAN_FM1R_FBM24_Pos (24U)
2293 #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2294 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2295 #define CAN_FM1R_FBM25_Pos (25U)
2296 #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2297 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2298 #define CAN_FM1R_FBM26_Pos (26U)
2299 #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2300 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2301 #define CAN_FM1R_FBM27_Pos (27U)
2302 #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2303 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2305 /******************* Bit definition for CAN_FS1R register *******************/
2306 #define CAN_FS1R_FSC_Pos (0U)
2307 #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2308 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2309 #define CAN_FS1R_FSC0_Pos (0U)
2310 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2311 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2312 #define CAN_FS1R_FSC1_Pos (1U)
2313 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2314 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2315 #define CAN_FS1R_FSC2_Pos (2U)
2316 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2317 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2318 #define CAN_FS1R_FSC3_Pos (3U)
2319 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2320 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2321 #define CAN_FS1R_FSC4_Pos (4U)
2322 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2323 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2324 #define CAN_FS1R_FSC5_Pos (5U)
2325 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2326 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2327 #define CAN_FS1R_FSC6_Pos (6U)
2328 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2329 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2330 #define CAN_FS1R_FSC7_Pos (7U)
2331 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2332 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2333 #define CAN_FS1R_FSC8_Pos (8U)
2334 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2335 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2336 #define CAN_FS1R_FSC9_Pos (9U)
2337 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2338 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2339 #define CAN_FS1R_FSC10_Pos (10U)
2340 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2341 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2342 #define CAN_FS1R_FSC11_Pos (11U)
2343 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2344 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2345 #define CAN_FS1R_FSC12_Pos (12U)
2346 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2347 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2348 #define CAN_FS1R_FSC13_Pos (13U)
2349 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2350 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2351 #define CAN_FS1R_FSC14_Pos (14U)
2352 #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2353 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2354 #define CAN_FS1R_FSC15_Pos (15U)
2355 #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2356 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2357 #define CAN_FS1R_FSC16_Pos (16U)
2358 #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2359 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2360 #define CAN_FS1R_FSC17_Pos (17U)
2361 #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2362 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2363 #define CAN_FS1R_FSC18_Pos (18U)
2364 #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2365 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2366 #define CAN_FS1R_FSC19_Pos (19U)
2367 #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2368 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2369 #define CAN_FS1R_FSC20_Pos (20U)
2370 #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2371 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2372 #define CAN_FS1R_FSC21_Pos (21U)
2373 #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2374 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2375 #define CAN_FS1R_FSC22_Pos (22U)
2376 #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2377 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2378 #define CAN_FS1R_FSC23_Pos (23U)
2379 #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2380 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2381 #define CAN_FS1R_FSC24_Pos (24U)
2382 #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2383 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2384 #define CAN_FS1R_FSC25_Pos (25U)
2385 #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2386 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2387 #define CAN_FS1R_FSC26_Pos (26U)
2388 #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2389 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2390 #define CAN_FS1R_FSC27_Pos (27U)
2391 #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2392 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2394 /****************** Bit definition for CAN_FFA1R register *******************/
2395 #define CAN_FFA1R_FFA_Pos (0U)
2396 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2397 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2398 #define CAN_FFA1R_FFA0_Pos (0U)
2399 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2400 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2401 #define CAN_FFA1R_FFA1_Pos (1U)
2402 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2403 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2404 #define CAN_FFA1R_FFA2_Pos (2U)
2405 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2406 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2407 #define CAN_FFA1R_FFA3_Pos (3U)
2408 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2409 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2410 #define CAN_FFA1R_FFA4_Pos (4U)
2411 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2412 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2413 #define CAN_FFA1R_FFA5_Pos (5U)
2414 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2415 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2416 #define CAN_FFA1R_FFA6_Pos (6U)
2417 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2418 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2419 #define CAN_FFA1R_FFA7_Pos (7U)
2420 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2421 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2422 #define CAN_FFA1R_FFA8_Pos (8U)
2423 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2424 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2425 #define CAN_FFA1R_FFA9_Pos (9U)
2426 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2427 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2428 #define CAN_FFA1R_FFA10_Pos (10U)
2429 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2430 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2431 #define CAN_FFA1R_FFA11_Pos (11U)
2432 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2433 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2434 #define CAN_FFA1R_FFA12_Pos (12U)
2435 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2436 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2437 #define CAN_FFA1R_FFA13_Pos (13U)
2438 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2439 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2440 #define CAN_FFA1R_FFA14_Pos (14U)
2441 #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2442 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2443 #define CAN_FFA1R_FFA15_Pos (15U)
2444 #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2445 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2446 #define CAN_FFA1R_FFA16_Pos (16U)
2447 #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2448 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2449 #define CAN_FFA1R_FFA17_Pos (17U)
2450 #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2451 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2452 #define CAN_FFA1R_FFA18_Pos (18U)
2453 #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2454 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2455 #define CAN_FFA1R_FFA19_Pos (19U)
2456 #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2457 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2458 #define CAN_FFA1R_FFA20_Pos (20U)
2459 #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2460 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2461 #define CAN_FFA1R_FFA21_Pos (21U)
2462 #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2463 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2464 #define CAN_FFA1R_FFA22_Pos (22U)
2465 #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2466 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2467 #define CAN_FFA1R_FFA23_Pos (23U)
2468 #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2469 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2470 #define CAN_FFA1R_FFA24_Pos (24U)
2471 #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2472 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2473 #define CAN_FFA1R_FFA25_Pos (25U)
2474 #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2475 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2476 #define CAN_FFA1R_FFA26_Pos (26U)
2477 #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2478 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2479 #define CAN_FFA1R_FFA27_Pos (27U)
2480 #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2481 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2483 /******************* Bit definition for CAN_FA1R register *******************/
2484 #define CAN_FA1R_FACT_Pos (0U)
2485 #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2486 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2487 #define CAN_FA1R_FACT0_Pos (0U)
2488 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2489 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2490 #define CAN_FA1R_FACT1_Pos (1U)
2491 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2492 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2493 #define CAN_FA1R_FACT2_Pos (2U)
2494 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2495 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2496 #define CAN_FA1R_FACT3_Pos (3U)
2497 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2498 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2499 #define CAN_FA1R_FACT4_Pos (4U)
2500 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2501 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2502 #define CAN_FA1R_FACT5_Pos (5U)
2503 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2504 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2505 #define CAN_FA1R_FACT6_Pos (6U)
2506 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2507 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2508 #define CAN_FA1R_FACT7_Pos (7U)
2509 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2510 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2511 #define CAN_FA1R_FACT8_Pos (8U)
2512 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2513 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2514 #define CAN_FA1R_FACT9_Pos (9U)
2515 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2516 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2517 #define CAN_FA1R_FACT10_Pos (10U)
2518 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2519 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2520 #define CAN_FA1R_FACT11_Pos (11U)
2521 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2522 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2523 #define CAN_FA1R_FACT12_Pos (12U)
2524 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2525 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2526 #define CAN_FA1R_FACT13_Pos (13U)
2527 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2528 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2529 #define CAN_FA1R_FACT14_Pos (14U)
2530 #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2531 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2532 #define CAN_FA1R_FACT15_Pos (15U)
2533 #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2534 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2535 #define CAN_FA1R_FACT16_Pos (16U)
2536 #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2537 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2538 #define CAN_FA1R_FACT17_Pos (17U)
2539 #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2540 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2541 #define CAN_FA1R_FACT18_Pos (18U)
2542 #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2543 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2544 #define CAN_FA1R_FACT19_Pos (19U)
2545 #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2546 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2547 #define CAN_FA1R_FACT20_Pos (20U)
2548 #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2549 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2550 #define CAN_FA1R_FACT21_Pos (21U)
2551 #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2552 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2553 #define CAN_FA1R_FACT22_Pos (22U)
2554 #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2555 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2556 #define CAN_FA1R_FACT23_Pos (23U)
2557 #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2558 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2559 #define CAN_FA1R_FACT24_Pos (24U)
2560 #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2561 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2562 #define CAN_FA1R_FACT25_Pos (25U)
2563 #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2564 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2565 #define CAN_FA1R_FACT26_Pos (26U)
2566 #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2567 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2568 #define CAN_FA1R_FACT27_Pos (27U)
2569 #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2570 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2573 /******************* Bit definition for CAN_F0R1 register *******************/
2574 #define CAN_F0R1_FB0_Pos (0U)
2575 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2576 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2577 #define CAN_F0R1_FB1_Pos (1U)
2578 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2579 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2580 #define CAN_F0R1_FB2_Pos (2U)
2581 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2582 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2583 #define CAN_F0R1_FB3_Pos (3U)
2584 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2585 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2586 #define CAN_F0R1_FB4_Pos (4U)
2587 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2588 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2589 #define CAN_F0R1_FB5_Pos (5U)
2590 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2591 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2592 #define CAN_F0R1_FB6_Pos (6U)
2593 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2594 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2595 #define CAN_F0R1_FB7_Pos (7U)
2596 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2597 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2598 #define CAN_F0R1_FB8_Pos (8U)
2599 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2600 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2601 #define CAN_F0R1_FB9_Pos (9U)
2602 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2603 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2604 #define CAN_F0R1_FB10_Pos (10U)
2605 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2606 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2607 #define CAN_F0R1_FB11_Pos (11U)
2608 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2609 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2610 #define CAN_F0R1_FB12_Pos (12U)
2611 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2612 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2613 #define CAN_F0R1_FB13_Pos (13U)
2614 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2615 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2616 #define CAN_F0R1_FB14_Pos (14U)
2617 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2618 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2619 #define CAN_F0R1_FB15_Pos (15U)
2620 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2621 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2622 #define CAN_F0R1_FB16_Pos (16U)
2623 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2624 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2625 #define CAN_F0R1_FB17_Pos (17U)
2626 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2627 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2628 #define CAN_F0R1_FB18_Pos (18U)
2629 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2630 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2631 #define CAN_F0R1_FB19_Pos (19U)
2632 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2633 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2634 #define CAN_F0R1_FB20_Pos (20U)
2635 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2636 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2637 #define CAN_F0R1_FB21_Pos (21U)
2638 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2639 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2640 #define CAN_F0R1_FB22_Pos (22U)
2641 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2642 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2643 #define CAN_F0R1_FB23_Pos (23U)
2644 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2645 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2646 #define CAN_F0R1_FB24_Pos (24U)
2647 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2648 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2649 #define CAN_F0R1_FB25_Pos (25U)
2650 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2651 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2652 #define CAN_F0R1_FB26_Pos (26U)
2653 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2654 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2655 #define CAN_F0R1_FB27_Pos (27U)
2656 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2657 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2658 #define CAN_F0R1_FB28_Pos (28U)
2659 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2660 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2661 #define CAN_F0R1_FB29_Pos (29U)
2662 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2663 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2664 #define CAN_F0R1_FB30_Pos (30U)
2665 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2666 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2667 #define CAN_F0R1_FB31_Pos (31U)
2668 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2669 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2671 /******************* Bit definition for CAN_F1R1 register *******************/
2672 #define CAN_F1R1_FB0_Pos (0U)
2673 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2674 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2675 #define CAN_F1R1_FB1_Pos (1U)
2676 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2677 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2678 #define CAN_F1R1_FB2_Pos (2U)
2679 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2680 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2681 #define CAN_F1R1_FB3_Pos (3U)
2682 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2683 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2684 #define CAN_F1R1_FB4_Pos (4U)
2685 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2686 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2687 #define CAN_F1R1_FB5_Pos (5U)
2688 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2689 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2690 #define CAN_F1R1_FB6_Pos (6U)
2691 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2692 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2693 #define CAN_F1R1_FB7_Pos (7U)
2694 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2695 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2696 #define CAN_F1R1_FB8_Pos (8U)
2697 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2698 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2699 #define CAN_F1R1_FB9_Pos (9U)
2700 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2701 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2702 #define CAN_F1R1_FB10_Pos (10U)
2703 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2704 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2705 #define CAN_F1R1_FB11_Pos (11U)
2706 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2707 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2708 #define CAN_F1R1_FB12_Pos (12U)
2709 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2710 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2711 #define CAN_F1R1_FB13_Pos (13U)
2712 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2713 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2714 #define CAN_F1R1_FB14_Pos (14U)
2715 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2716 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2717 #define CAN_F1R1_FB15_Pos (15U)
2718 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2719 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2720 #define CAN_F1R1_FB16_Pos (16U)
2721 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2722 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2723 #define CAN_F1R1_FB17_Pos (17U)
2724 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2725 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2726 #define CAN_F1R1_FB18_Pos (18U)
2727 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2728 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2729 #define CAN_F1R1_FB19_Pos (19U)
2730 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2731 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2732 #define CAN_F1R1_FB20_Pos (20U)
2733 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2734 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2735 #define CAN_F1R1_FB21_Pos (21U)
2736 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2737 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2738 #define CAN_F1R1_FB22_Pos (22U)
2739 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2740 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2741 #define CAN_F1R1_FB23_Pos (23U)
2742 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2743 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2744 #define CAN_F1R1_FB24_Pos (24U)
2745 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2746 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2747 #define CAN_F1R1_FB25_Pos (25U)
2748 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2749 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2750 #define CAN_F1R1_FB26_Pos (26U)
2751 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2752 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2753 #define CAN_F1R1_FB27_Pos (27U)
2754 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2755 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2756 #define CAN_F1R1_FB28_Pos (28U)
2757 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2758 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2759 #define CAN_F1R1_FB29_Pos (29U)
2760 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2761 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2762 #define CAN_F1R1_FB30_Pos (30U)
2763 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2764 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2765 #define CAN_F1R1_FB31_Pos (31U)
2766 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2767 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2769 /******************* Bit definition for CAN_F2R1 register *******************/
2770 #define CAN_F2R1_FB0_Pos (0U)
2771 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2772 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2773 #define CAN_F2R1_FB1_Pos (1U)
2774 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2775 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2776 #define CAN_F2R1_FB2_Pos (2U)
2777 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2778 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2779 #define CAN_F2R1_FB3_Pos (3U)
2780 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2781 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2782 #define CAN_F2R1_FB4_Pos (4U)
2783 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2784 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2785 #define CAN_F2R1_FB5_Pos (5U)
2786 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2787 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2788 #define CAN_F2R1_FB6_Pos (6U)
2789 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2790 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2791 #define CAN_F2R1_FB7_Pos (7U)
2792 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2793 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2794 #define CAN_F2R1_FB8_Pos (8U)
2795 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2796 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2797 #define CAN_F2R1_FB9_Pos (9U)
2798 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2799 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2800 #define CAN_F2R1_FB10_Pos (10U)
2801 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2802 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2803 #define CAN_F2R1_FB11_Pos (11U)
2804 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2805 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2806 #define CAN_F2R1_FB12_Pos (12U)
2807 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2808 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2809 #define CAN_F2R1_FB13_Pos (13U)
2810 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2811 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2812 #define CAN_F2R1_FB14_Pos (14U)
2813 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2814 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2815 #define CAN_F2R1_FB15_Pos (15U)
2816 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2817 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2818 #define CAN_F2R1_FB16_Pos (16U)
2819 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2820 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2821 #define CAN_F2R1_FB17_Pos (17U)
2822 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2823 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2824 #define CAN_F2R1_FB18_Pos (18U)
2825 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2826 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2827 #define CAN_F2R1_FB19_Pos (19U)
2828 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2829 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2830 #define CAN_F2R1_FB20_Pos (20U)
2831 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2832 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2833 #define CAN_F2R1_FB21_Pos (21U)
2834 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2835 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2836 #define CAN_F2R1_FB22_Pos (22U)
2837 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2838 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2839 #define CAN_F2R1_FB23_Pos (23U)
2840 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2841 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2842 #define CAN_F2R1_FB24_Pos (24U)
2843 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2844 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2845 #define CAN_F2R1_FB25_Pos (25U)
2846 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2847 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2848 #define CAN_F2R1_FB26_Pos (26U)
2849 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2850 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2851 #define CAN_F2R1_FB27_Pos (27U)
2852 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2853 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2854 #define CAN_F2R1_FB28_Pos (28U)
2855 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2856 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2857 #define CAN_F2R1_FB29_Pos (29U)
2858 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2859 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2860 #define CAN_F2R1_FB30_Pos (30U)
2861 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2862 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2863 #define CAN_F2R1_FB31_Pos (31U)
2864 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2865 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2867 /******************* Bit definition for CAN_F3R1 register *******************/
2868 #define CAN_F3R1_FB0_Pos (0U)
2869 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2870 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2871 #define CAN_F3R1_FB1_Pos (1U)
2872 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2873 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2874 #define CAN_F3R1_FB2_Pos (2U)
2875 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2876 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2877 #define CAN_F3R1_FB3_Pos (3U)
2878 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2879 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2880 #define CAN_F3R1_FB4_Pos (4U)
2881 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2882 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2883 #define CAN_F3R1_FB5_Pos (5U)
2884 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2885 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2886 #define CAN_F3R1_FB6_Pos (6U)
2887 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2888 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2889 #define CAN_F3R1_FB7_Pos (7U)
2890 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
2891 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
2892 #define CAN_F3R1_FB8_Pos (8U)
2893 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
2894 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
2895 #define CAN_F3R1_FB9_Pos (9U)
2896 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
2897 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
2898 #define CAN_F3R1_FB10_Pos (10U)
2899 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
2900 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
2901 #define CAN_F3R1_FB11_Pos (11U)
2902 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
2903 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
2904 #define CAN_F3R1_FB12_Pos (12U)
2905 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
2906 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
2907 #define CAN_F3R1_FB13_Pos (13U)
2908 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
2909 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
2910 #define CAN_F3R1_FB14_Pos (14U)
2911 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
2912 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
2913 #define CAN_F3R1_FB15_Pos (15U)
2914 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
2915 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
2916 #define CAN_F3R1_FB16_Pos (16U)
2917 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
2918 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
2919 #define CAN_F3R1_FB17_Pos (17U)
2920 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
2921 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
2922 #define CAN_F3R1_FB18_Pos (18U)
2923 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
2924 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
2925 #define CAN_F3R1_FB19_Pos (19U)
2926 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
2927 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
2928 #define CAN_F3R1_FB20_Pos (20U)
2929 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
2930 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
2931 #define CAN_F3R1_FB21_Pos (21U)
2932 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
2933 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
2934 #define CAN_F3R1_FB22_Pos (22U)
2935 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
2936 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
2937 #define CAN_F3R1_FB23_Pos (23U)
2938 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
2939 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
2940 #define CAN_F3R1_FB24_Pos (24U)
2941 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
2942 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
2943 #define CAN_F3R1_FB25_Pos (25U)
2944 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
2945 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
2946 #define CAN_F3R1_FB26_Pos (26U)
2947 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
2948 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
2949 #define CAN_F3R1_FB27_Pos (27U)
2950 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
2951 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
2952 #define CAN_F3R1_FB28_Pos (28U)
2953 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
2954 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
2955 #define CAN_F3R1_FB29_Pos (29U)
2956 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
2957 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
2958 #define CAN_F3R1_FB30_Pos (30U)
2959 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
2960 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
2961 #define CAN_F3R1_FB31_Pos (31U)
2962 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
2963 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
2965 /******************* Bit definition for CAN_F4R1 register *******************/
2966 #define CAN_F4R1_FB0_Pos (0U)
2967 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
2968 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
2969 #define CAN_F4R1_FB1_Pos (1U)
2970 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
2971 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
2972 #define CAN_F4R1_FB2_Pos (2U)
2973 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
2974 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
2975 #define CAN_F4R1_FB3_Pos (3U)
2976 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
2977 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
2978 #define CAN_F4R1_FB4_Pos (4U)
2979 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
2980 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
2981 #define CAN_F4R1_FB5_Pos (5U)
2982 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
2983 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
2984 #define CAN_F4R1_FB6_Pos (6U)
2985 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
2986 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
2987 #define CAN_F4R1_FB7_Pos (7U)
2988 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
2989 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
2990 #define CAN_F4R1_FB8_Pos (8U)
2991 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
2992 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
2993 #define CAN_F4R1_FB9_Pos (9U)
2994 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
2995 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
2996 #define CAN_F4R1_FB10_Pos (10U)
2997 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
2998 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
2999 #define CAN_F4R1_FB11_Pos (11U)
3000 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3001 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3002 #define CAN_F4R1_FB12_Pos (12U)
3003 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3004 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3005 #define CAN_F4R1_FB13_Pos (13U)
3006 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3007 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3008 #define CAN_F4R1_FB14_Pos (14U)
3009 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3010 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3011 #define CAN_F4R1_FB15_Pos (15U)
3012 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3013 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3014 #define CAN_F4R1_FB16_Pos (16U)
3015 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3016 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3017 #define CAN_F4R1_FB17_Pos (17U)
3018 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3019 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3020 #define CAN_F4R1_FB18_Pos (18U)
3021 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3022 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3023 #define CAN_F4R1_FB19_Pos (19U)
3024 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3025 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3026 #define CAN_F4R1_FB20_Pos (20U)
3027 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3028 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3029 #define CAN_F4R1_FB21_Pos (21U)
3030 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3031 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3032 #define CAN_F4R1_FB22_Pos (22U)
3033 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3034 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3035 #define CAN_F4R1_FB23_Pos (23U)
3036 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3037 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3038 #define CAN_F4R1_FB24_Pos (24U)
3039 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3040 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3041 #define CAN_F4R1_FB25_Pos (25U)
3042 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3043 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3044 #define CAN_F4R1_FB26_Pos (26U)
3045 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3046 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3047 #define CAN_F4R1_FB27_Pos (27U)
3048 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3049 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3050 #define CAN_F4R1_FB28_Pos (28U)
3051 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3052 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3053 #define CAN_F4R1_FB29_Pos (29U)
3054 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3055 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3056 #define CAN_F4R1_FB30_Pos (30U)
3057 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3058 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3059 #define CAN_F4R1_FB31_Pos (31U)
3060 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3061 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3063 /******************* Bit definition for CAN_F5R1 register *******************/
3064 #define CAN_F5R1_FB0_Pos (0U)
3065 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3066 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3067 #define CAN_F5R1_FB1_Pos (1U)
3068 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3069 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3070 #define CAN_F5R1_FB2_Pos (2U)
3071 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3072 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3073 #define CAN_F5R1_FB3_Pos (3U)
3074 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3075 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3076 #define CAN_F5R1_FB4_Pos (4U)
3077 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3078 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3079 #define CAN_F5R1_FB5_Pos (5U)
3080 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3081 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3082 #define CAN_F5R1_FB6_Pos (6U)
3083 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3084 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3085 #define CAN_F5R1_FB7_Pos (7U)
3086 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3087 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3088 #define CAN_F5R1_FB8_Pos (8U)
3089 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3090 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3091 #define CAN_F5R1_FB9_Pos (9U)
3092 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3093 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3094 #define CAN_F5R1_FB10_Pos (10U)
3095 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3096 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3097 #define CAN_F5R1_FB11_Pos (11U)
3098 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3099 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3100 #define CAN_F5R1_FB12_Pos (12U)
3101 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3102 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3103 #define CAN_F5R1_FB13_Pos (13U)
3104 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3105 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3106 #define CAN_F5R1_FB14_Pos (14U)
3107 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3108 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3109 #define CAN_F5R1_FB15_Pos (15U)
3110 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3111 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3112 #define CAN_F5R1_FB16_Pos (16U)
3113 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3114 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3115 #define CAN_F5R1_FB17_Pos (17U)
3116 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3117 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3118 #define CAN_F5R1_FB18_Pos (18U)
3119 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3120 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3121 #define CAN_F5R1_FB19_Pos (19U)
3122 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3123 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3124 #define CAN_F5R1_FB20_Pos (20U)
3125 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3126 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3127 #define CAN_F5R1_FB21_Pos (21U)
3128 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3129 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3130 #define CAN_F5R1_FB22_Pos (22U)
3131 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3132 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3133 #define CAN_F5R1_FB23_Pos (23U)
3134 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3135 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3136 #define CAN_F5R1_FB24_Pos (24U)
3137 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3138 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3139 #define CAN_F5R1_FB25_Pos (25U)
3140 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3141 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3142 #define CAN_F5R1_FB26_Pos (26U)
3143 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3144 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3145 #define CAN_F5R1_FB27_Pos (27U)
3146 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3147 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3148 #define CAN_F5R1_FB28_Pos (28U)
3149 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3150 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3151 #define CAN_F5R1_FB29_Pos (29U)
3152 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3153 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3154 #define CAN_F5R1_FB30_Pos (30U)
3155 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3156 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3157 #define CAN_F5R1_FB31_Pos (31U)
3158 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3159 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3161 /******************* Bit definition for CAN_F6R1 register *******************/
3162 #define CAN_F6R1_FB0_Pos (0U)
3163 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3164 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3165 #define CAN_F6R1_FB1_Pos (1U)
3166 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3167 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3168 #define CAN_F6R1_FB2_Pos (2U)
3169 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3170 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3171 #define CAN_F6R1_FB3_Pos (3U)
3172 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3173 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3174 #define CAN_F6R1_FB4_Pos (4U)
3175 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3176 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3177 #define CAN_F6R1_FB5_Pos (5U)
3178 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3179 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3180 #define CAN_F6R1_FB6_Pos (6U)
3181 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3182 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3183 #define CAN_F6R1_FB7_Pos (7U)
3184 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3185 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3186 #define CAN_F6R1_FB8_Pos (8U)
3187 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3188 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3189 #define CAN_F6R1_FB9_Pos (9U)
3190 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3191 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3192 #define CAN_F6R1_FB10_Pos (10U)
3193 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3194 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3195 #define CAN_F6R1_FB11_Pos (11U)
3196 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3197 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3198 #define CAN_F6R1_FB12_Pos (12U)
3199 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3200 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3201 #define CAN_F6R1_FB13_Pos (13U)
3202 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3203 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3204 #define CAN_F6R1_FB14_Pos (14U)
3205 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3206 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3207 #define CAN_F6R1_FB15_Pos (15U)
3208 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3209 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3210 #define CAN_F6R1_FB16_Pos (16U)
3211 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3212 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3213 #define CAN_F6R1_FB17_Pos (17U)
3214 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3215 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3216 #define CAN_F6R1_FB18_Pos (18U)
3217 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3218 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3219 #define CAN_F6R1_FB19_Pos (19U)
3220 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3221 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3222 #define CAN_F6R1_FB20_Pos (20U)
3223 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3224 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3225 #define CAN_F6R1_FB21_Pos (21U)
3226 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3227 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3228 #define CAN_F6R1_FB22_Pos (22U)
3229 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3230 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3231 #define CAN_F6R1_FB23_Pos (23U)
3232 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3233 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3234 #define CAN_F6R1_FB24_Pos (24U)
3235 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3236 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3237 #define CAN_F6R1_FB25_Pos (25U)
3238 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3239 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3240 #define CAN_F6R1_FB26_Pos (26U)
3241 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3242 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3243 #define CAN_F6R1_FB27_Pos (27U)
3244 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3245 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3246 #define CAN_F6R1_FB28_Pos (28U)
3247 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3248 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3249 #define CAN_F6R1_FB29_Pos (29U)
3250 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3251 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3252 #define CAN_F6R1_FB30_Pos (30U)
3253 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3254 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3255 #define CAN_F6R1_FB31_Pos (31U)
3256 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3257 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3259 /******************* Bit definition for CAN_F7R1 register *******************/
3260 #define CAN_F7R1_FB0_Pos (0U)
3261 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3262 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3263 #define CAN_F7R1_FB1_Pos (1U)
3264 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3265 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3266 #define CAN_F7R1_FB2_Pos (2U)
3267 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3268 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3269 #define CAN_F7R1_FB3_Pos (3U)
3270 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3271 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3272 #define CAN_F7R1_FB4_Pos (4U)
3273 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3274 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3275 #define CAN_F7R1_FB5_Pos (5U)
3276 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3277 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3278 #define CAN_F7R1_FB6_Pos (6U)
3279 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3280 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3281 #define CAN_F7R1_FB7_Pos (7U)
3282 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3283 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3284 #define CAN_F7R1_FB8_Pos (8U)
3285 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3286 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3287 #define CAN_F7R1_FB9_Pos (9U)
3288 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3289 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3290 #define CAN_F7R1_FB10_Pos (10U)
3291 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3292 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3293 #define CAN_F7R1_FB11_Pos (11U)
3294 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3295 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3296 #define CAN_F7R1_FB12_Pos (12U)
3297 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3298 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3299 #define CAN_F7R1_FB13_Pos (13U)
3300 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3301 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3302 #define CAN_F7R1_FB14_Pos (14U)
3303 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3304 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3305 #define CAN_F7R1_FB15_Pos (15U)
3306 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3307 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3308 #define CAN_F7R1_FB16_Pos (16U)
3309 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3310 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3311 #define CAN_F7R1_FB17_Pos (17U)
3312 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3313 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3314 #define CAN_F7R1_FB18_Pos (18U)
3315 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3316 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3317 #define CAN_F7R1_FB19_Pos (19U)
3318 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3319 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3320 #define CAN_F7R1_FB20_Pos (20U)
3321 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3322 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3323 #define CAN_F7R1_FB21_Pos (21U)
3324 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3325 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3326 #define CAN_F7R1_FB22_Pos (22U)
3327 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3328 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3329 #define CAN_F7R1_FB23_Pos (23U)
3330 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3331 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3332 #define CAN_F7R1_FB24_Pos (24U)
3333 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3334 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3335 #define CAN_F7R1_FB25_Pos (25U)
3336 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3337 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3338 #define CAN_F7R1_FB26_Pos (26U)
3339 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3340 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3341 #define CAN_F7R1_FB27_Pos (27U)
3342 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3343 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3344 #define CAN_F7R1_FB28_Pos (28U)
3345 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3346 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3347 #define CAN_F7R1_FB29_Pos (29U)
3348 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3349 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3350 #define CAN_F7R1_FB30_Pos (30U)
3351 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3352 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3353 #define CAN_F7R1_FB31_Pos (31U)
3354 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3355 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3357 /******************* Bit definition for CAN_F8R1 register *******************/
3358 #define CAN_F8R1_FB0_Pos (0U)
3359 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3360 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3361 #define CAN_F8R1_FB1_Pos (1U)
3362 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3363 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3364 #define CAN_F8R1_FB2_Pos (2U)
3365 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3366 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3367 #define CAN_F8R1_FB3_Pos (3U)
3368 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3369 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3370 #define CAN_F8R1_FB4_Pos (4U)
3371 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3372 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3373 #define CAN_F8R1_FB5_Pos (5U)
3374 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3375 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3376 #define CAN_F8R1_FB6_Pos (6U)
3377 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3378 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3379 #define CAN_F8R1_FB7_Pos (7U)
3380 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3381 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3382 #define CAN_F8R1_FB8_Pos (8U)
3383 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3384 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3385 #define CAN_F8R1_FB9_Pos (9U)
3386 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3387 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3388 #define CAN_F8R1_FB10_Pos (10U)
3389 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3390 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3391 #define CAN_F8R1_FB11_Pos (11U)
3392 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3393 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3394 #define CAN_F8R1_FB12_Pos (12U)
3395 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3396 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3397 #define CAN_F8R1_FB13_Pos (13U)
3398 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3399 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3400 #define CAN_F8R1_FB14_Pos (14U)
3401 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3402 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3403 #define CAN_F8R1_FB15_Pos (15U)
3404 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3405 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3406 #define CAN_F8R1_FB16_Pos (16U)
3407 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3408 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3409 #define CAN_F8R1_FB17_Pos (17U)
3410 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3411 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3412 #define CAN_F8R1_FB18_Pos (18U)
3413 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3414 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3415 #define CAN_F8R1_FB19_Pos (19U)
3416 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3417 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3418 #define CAN_F8R1_FB20_Pos (20U)
3419 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3420 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3421 #define CAN_F8R1_FB21_Pos (21U)
3422 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3423 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3424 #define CAN_F8R1_FB22_Pos (22U)
3425 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3426 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3427 #define CAN_F8R1_FB23_Pos (23U)
3428 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3429 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3430 #define CAN_F8R1_FB24_Pos (24U)
3431 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3432 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3433 #define CAN_F8R1_FB25_Pos (25U)
3434 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3435 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3436 #define CAN_F8R1_FB26_Pos (26U)
3437 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3438 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3439 #define CAN_F8R1_FB27_Pos (27U)
3440 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3441 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3442 #define CAN_F8R1_FB28_Pos (28U)
3443 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3444 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3445 #define CAN_F8R1_FB29_Pos (29U)
3446 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3447 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3448 #define CAN_F8R1_FB30_Pos (30U)
3449 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3450 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3451 #define CAN_F8R1_FB31_Pos (31U)
3452 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3453 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3455 /******************* Bit definition for CAN_F9R1 register *******************/
3456 #define CAN_F9R1_FB0_Pos (0U)
3457 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3458 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3459 #define CAN_F9R1_FB1_Pos (1U)
3460 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3461 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3462 #define CAN_F9R1_FB2_Pos (2U)
3463 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3464 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3465 #define CAN_F9R1_FB3_Pos (3U)
3466 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3467 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3468 #define CAN_F9R1_FB4_Pos (4U)
3469 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3470 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3471 #define CAN_F9R1_FB5_Pos (5U)
3472 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3473 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3474 #define CAN_F9R1_FB6_Pos (6U)
3475 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3476 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3477 #define CAN_F9R1_FB7_Pos (7U)
3478 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3479 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3480 #define CAN_F9R1_FB8_Pos (8U)
3481 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3482 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3483 #define CAN_F9R1_FB9_Pos (9U)
3484 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3485 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3486 #define CAN_F9R1_FB10_Pos (10U)
3487 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3488 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3489 #define CAN_F9R1_FB11_Pos (11U)
3490 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3491 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3492 #define CAN_F9R1_FB12_Pos (12U)
3493 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3494 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3495 #define CAN_F9R1_FB13_Pos (13U)
3496 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3497 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3498 #define CAN_F9R1_FB14_Pos (14U)
3499 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3500 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3501 #define CAN_F9R1_FB15_Pos (15U)
3502 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3503 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3504 #define CAN_F9R1_FB16_Pos (16U)
3505 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3506 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3507 #define CAN_F9R1_FB17_Pos (17U)
3508 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3509 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3510 #define CAN_F9R1_FB18_Pos (18U)
3511 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3512 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3513 #define CAN_F9R1_FB19_Pos (19U)
3514 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3515 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3516 #define CAN_F9R1_FB20_Pos (20U)
3517 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3518 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3519 #define CAN_F9R1_FB21_Pos (21U)
3520 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3521 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3522 #define CAN_F9R1_FB22_Pos (22U)
3523 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3524 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3525 #define CAN_F9R1_FB23_Pos (23U)
3526 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3527 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3528 #define CAN_F9R1_FB24_Pos (24U)
3529 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3530 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3531 #define CAN_F9R1_FB25_Pos (25U)
3532 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3533 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3534 #define CAN_F9R1_FB26_Pos (26U)
3535 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3536 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3537 #define CAN_F9R1_FB27_Pos (27U)
3538 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3539 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3540 #define CAN_F9R1_FB28_Pos (28U)
3541 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3542 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3543 #define CAN_F9R1_FB29_Pos (29U)
3544 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3545 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3546 #define CAN_F9R1_FB30_Pos (30U)
3547 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3548 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3549 #define CAN_F9R1_FB31_Pos (31U)
3550 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3551 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3553 /******************* Bit definition for CAN_F10R1 register ******************/
3554 #define CAN_F10R1_FB0_Pos (0U)
3555 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3556 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3557 #define CAN_F10R1_FB1_Pos (1U)
3558 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3559 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3560 #define CAN_F10R1_FB2_Pos (2U)
3561 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3562 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3563 #define CAN_F10R1_FB3_Pos (3U)
3564 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3565 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3566 #define CAN_F10R1_FB4_Pos (4U)
3567 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3568 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3569 #define CAN_F10R1_FB5_Pos (5U)
3570 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3571 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3572 #define CAN_F10R1_FB6_Pos (6U)
3573 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3574 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3575 #define CAN_F10R1_FB7_Pos (7U)
3576 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3577 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3578 #define CAN_F10R1_FB8_Pos (8U)
3579 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3580 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3581 #define CAN_F10R1_FB9_Pos (9U)
3582 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3583 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3584 #define CAN_F10R1_FB10_Pos (10U)
3585 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3586 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3587 #define CAN_F10R1_FB11_Pos (11U)
3588 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3589 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3590 #define CAN_F10R1_FB12_Pos (12U)
3591 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3592 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3593 #define CAN_F10R1_FB13_Pos (13U)
3594 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3595 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3596 #define CAN_F10R1_FB14_Pos (14U)
3597 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3598 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3599 #define CAN_F10R1_FB15_Pos (15U)
3600 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3601 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3602 #define CAN_F10R1_FB16_Pos (16U)
3603 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3604 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3605 #define CAN_F10R1_FB17_Pos (17U)
3606 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3607 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3608 #define CAN_F10R1_FB18_Pos (18U)
3609 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3610 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3611 #define CAN_F10R1_FB19_Pos (19U)
3612 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3613 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3614 #define CAN_F10R1_FB20_Pos (20U)
3615 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3616 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3617 #define CAN_F10R1_FB21_Pos (21U)
3618 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3619 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3620 #define CAN_F10R1_FB22_Pos (22U)
3621 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3622 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3623 #define CAN_F10R1_FB23_Pos (23U)
3624 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3625 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3626 #define CAN_F10R1_FB24_Pos (24U)
3627 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3628 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3629 #define CAN_F10R1_FB25_Pos (25U)
3630 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3631 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3632 #define CAN_F10R1_FB26_Pos (26U)
3633 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3634 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3635 #define CAN_F10R1_FB27_Pos (27U)
3636 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3637 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3638 #define CAN_F10R1_FB28_Pos (28U)
3639 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3640 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3641 #define CAN_F10R1_FB29_Pos (29U)
3642 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3643 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3644 #define CAN_F10R1_FB30_Pos (30U)
3645 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3646 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3647 #define CAN_F10R1_FB31_Pos (31U)
3648 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3649 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3651 /******************* Bit definition for CAN_F11R1 register ******************/
3652 #define CAN_F11R1_FB0_Pos (0U)
3653 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3654 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3655 #define CAN_F11R1_FB1_Pos (1U)
3656 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3657 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3658 #define CAN_F11R1_FB2_Pos (2U)
3659 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3660 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3661 #define CAN_F11R1_FB3_Pos (3U)
3662 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3663 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3664 #define CAN_F11R1_FB4_Pos (4U)
3665 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3666 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3667 #define CAN_F11R1_FB5_Pos (5U)
3668 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3669 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3670 #define CAN_F11R1_FB6_Pos (6U)
3671 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3672 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3673 #define CAN_F11R1_FB7_Pos (7U)
3674 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3675 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3676 #define CAN_F11R1_FB8_Pos (8U)
3677 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3678 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3679 #define CAN_F11R1_FB9_Pos (9U)
3680 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3681 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3682 #define CAN_F11R1_FB10_Pos (10U)
3683 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3684 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3685 #define CAN_F11R1_FB11_Pos (11U)
3686 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3687 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3688 #define CAN_F11R1_FB12_Pos (12U)
3689 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3690 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3691 #define CAN_F11R1_FB13_Pos (13U)
3692 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3693 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3694 #define CAN_F11R1_FB14_Pos (14U)
3695 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3696 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3697 #define CAN_F11R1_FB15_Pos (15U)
3698 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3699 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3700 #define CAN_F11R1_FB16_Pos (16U)
3701 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3702 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3703 #define CAN_F11R1_FB17_Pos (17U)
3704 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3705 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3706 #define CAN_F11R1_FB18_Pos (18U)
3707 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3708 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3709 #define CAN_F11R1_FB19_Pos (19U)
3710 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3711 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3712 #define CAN_F11R1_FB20_Pos (20U)
3713 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3714 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3715 #define CAN_F11R1_FB21_Pos (21U)
3716 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3717 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3718 #define CAN_F11R1_FB22_Pos (22U)
3719 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3720 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3721 #define CAN_F11R1_FB23_Pos (23U)
3722 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3723 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3724 #define CAN_F11R1_FB24_Pos (24U)
3725 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3726 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3727 #define CAN_F11R1_FB25_Pos (25U)
3728 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3729 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3730 #define CAN_F11R1_FB26_Pos (26U)
3731 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3732 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3733 #define CAN_F11R1_FB27_Pos (27U)
3734 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3735 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3736 #define CAN_F11R1_FB28_Pos (28U)
3737 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3738 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3739 #define CAN_F11R1_FB29_Pos (29U)
3740 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3741 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3742 #define CAN_F11R1_FB30_Pos (30U)
3743 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3744 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3745 #define CAN_F11R1_FB31_Pos (31U)
3746 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3747 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3749 /******************* Bit definition for CAN_F12R1 register ******************/
3750 #define CAN_F12R1_FB0_Pos (0U)
3751 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3752 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3753 #define CAN_F12R1_FB1_Pos (1U)
3754 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3755 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3756 #define CAN_F12R1_FB2_Pos (2U)
3757 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3758 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3759 #define CAN_F12R1_FB3_Pos (3U)
3760 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3761 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3762 #define CAN_F12R1_FB4_Pos (4U)
3763 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3764 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3765 #define CAN_F12R1_FB5_Pos (5U)
3766 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3767 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3768 #define CAN_F12R1_FB6_Pos (6U)
3769 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3770 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3771 #define CAN_F12R1_FB7_Pos (7U)
3772 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3773 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3774 #define CAN_F12R1_FB8_Pos (8U)
3775 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3776 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3777 #define CAN_F12R1_FB9_Pos (9U)
3778 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3779 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3780 #define CAN_F12R1_FB10_Pos (10U)
3781 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3782 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3783 #define CAN_F12R1_FB11_Pos (11U)
3784 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3785 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3786 #define CAN_F12R1_FB12_Pos (12U)
3787 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3788 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3789 #define CAN_F12R1_FB13_Pos (13U)
3790 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3791 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3792 #define CAN_F12R1_FB14_Pos (14U)
3793 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3794 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3795 #define CAN_F12R1_FB15_Pos (15U)
3796 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3797 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3798 #define CAN_F12R1_FB16_Pos (16U)
3799 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3800 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3801 #define CAN_F12R1_FB17_Pos (17U)
3802 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3803 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3804 #define CAN_F12R1_FB18_Pos (18U)
3805 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3806 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3807 #define CAN_F12R1_FB19_Pos (19U)
3808 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3809 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3810 #define CAN_F12R1_FB20_Pos (20U)
3811 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3812 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3813 #define CAN_F12R1_FB21_Pos (21U)
3814 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3815 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3816 #define CAN_F12R1_FB22_Pos (22U)
3817 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3818 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3819 #define CAN_F12R1_FB23_Pos (23U)
3820 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3821 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3822 #define CAN_F12R1_FB24_Pos (24U)
3823 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3824 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3825 #define CAN_F12R1_FB25_Pos (25U)
3826 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3827 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3828 #define CAN_F12R1_FB26_Pos (26U)
3829 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3830 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3831 #define CAN_F12R1_FB27_Pos (27U)
3832 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3833 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3834 #define CAN_F12R1_FB28_Pos (28U)
3835 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3836 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3837 #define CAN_F12R1_FB29_Pos (29U)
3838 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3839 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3840 #define CAN_F12R1_FB30_Pos (30U)
3841 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3842 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3843 #define CAN_F12R1_FB31_Pos (31U)
3844 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3845 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3847 /******************* Bit definition for CAN_F13R1 register ******************/
3848 #define CAN_F13R1_FB0_Pos (0U)
3849 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3850 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3851 #define CAN_F13R1_FB1_Pos (1U)
3852 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3853 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3854 #define CAN_F13R1_FB2_Pos (2U)
3855 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3856 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3857 #define CAN_F13R1_FB3_Pos (3U)
3858 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3859 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3860 #define CAN_F13R1_FB4_Pos (4U)
3861 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3862 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3863 #define CAN_F13R1_FB5_Pos (5U)
3864 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3865 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3866 #define CAN_F13R1_FB6_Pos (6U)
3867 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3868 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3869 #define CAN_F13R1_FB7_Pos (7U)
3870 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3871 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3872 #define CAN_F13R1_FB8_Pos (8U)
3873 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3874 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3875 #define CAN_F13R1_FB9_Pos (9U)
3876 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3877 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3878 #define CAN_F13R1_FB10_Pos (10U)
3879 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3880 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3881 #define CAN_F13R1_FB11_Pos (11U)
3882 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3883 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3884 #define CAN_F13R1_FB12_Pos (12U)
3885 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3886 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3887 #define CAN_F13R1_FB13_Pos (13U)
3888 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3889 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
3890 #define CAN_F13R1_FB14_Pos (14U)
3891 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
3892 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
3893 #define CAN_F13R1_FB15_Pos (15U)
3894 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
3895 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
3896 #define CAN_F13R1_FB16_Pos (16U)
3897 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
3898 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
3899 #define CAN_F13R1_FB17_Pos (17U)
3900 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
3901 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
3902 #define CAN_F13R1_FB18_Pos (18U)
3903 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
3904 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
3905 #define CAN_F13R1_FB19_Pos (19U)
3906 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
3907 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
3908 #define CAN_F13R1_FB20_Pos (20U)
3909 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
3910 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
3911 #define CAN_F13R1_FB21_Pos (21U)
3912 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
3913 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
3914 #define CAN_F13R1_FB22_Pos (22U)
3915 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
3916 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
3917 #define CAN_F13R1_FB23_Pos (23U)
3918 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
3919 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
3920 #define CAN_F13R1_FB24_Pos (24U)
3921 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
3922 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
3923 #define CAN_F13R1_FB25_Pos (25U)
3924 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
3925 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
3926 #define CAN_F13R1_FB26_Pos (26U)
3927 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
3928 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
3929 #define CAN_F13R1_FB27_Pos (27U)
3930 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
3931 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
3932 #define CAN_F13R1_FB28_Pos (28U)
3933 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
3934 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
3935 #define CAN_F13R1_FB29_Pos (29U)
3936 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
3937 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
3938 #define CAN_F13R1_FB30_Pos (30U)
3939 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
3940 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
3941 #define CAN_F13R1_FB31_Pos (31U)
3942 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
3943 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
3945 /******************* Bit definition for CAN_F0R2 register *******************/
3946 #define CAN_F0R2_FB0_Pos (0U)
3947 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
3948 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
3949 #define CAN_F0R2_FB1_Pos (1U)
3950 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
3951 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
3952 #define CAN_F0R2_FB2_Pos (2U)
3953 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
3954 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
3955 #define CAN_F0R2_FB3_Pos (3U)
3956 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
3957 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
3958 #define CAN_F0R2_FB4_Pos (4U)
3959 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
3960 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
3961 #define CAN_F0R2_FB5_Pos (5U)
3962 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
3963 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
3964 #define CAN_F0R2_FB6_Pos (6U)
3965 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
3966 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
3967 #define CAN_F0R2_FB7_Pos (7U)
3968 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
3969 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
3970 #define CAN_F0R2_FB8_Pos (8U)
3971 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
3972 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
3973 #define CAN_F0R2_FB9_Pos (9U)
3974 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
3975 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
3976 #define CAN_F0R2_FB10_Pos (10U)
3977 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
3978 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
3979 #define CAN_F0R2_FB11_Pos (11U)
3980 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
3981 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
3982 #define CAN_F0R2_FB12_Pos (12U)
3983 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
3984 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
3985 #define CAN_F0R2_FB13_Pos (13U)
3986 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
3987 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
3988 #define CAN_F0R2_FB14_Pos (14U)
3989 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
3990 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
3991 #define CAN_F0R2_FB15_Pos (15U)
3992 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
3993 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
3994 #define CAN_F0R2_FB16_Pos (16U)
3995 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
3996 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
3997 #define CAN_F0R2_FB17_Pos (17U)
3998 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
3999 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4000 #define CAN_F0R2_FB18_Pos (18U)
4001 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4002 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4003 #define CAN_F0R2_FB19_Pos (19U)
4004 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4005 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4006 #define CAN_F0R2_FB20_Pos (20U)
4007 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4008 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4009 #define CAN_F0R2_FB21_Pos (21U)
4010 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4011 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4012 #define CAN_F0R2_FB22_Pos (22U)
4013 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4014 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4015 #define CAN_F0R2_FB23_Pos (23U)
4016 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4017 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4018 #define CAN_F0R2_FB24_Pos (24U)
4019 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4020 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4021 #define CAN_F0R2_FB25_Pos (25U)
4022 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4023 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4024 #define CAN_F0R2_FB26_Pos (26U)
4025 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4026 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4027 #define CAN_F0R2_FB27_Pos (27U)
4028 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4029 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4030 #define CAN_F0R2_FB28_Pos (28U)
4031 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4032 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4033 #define CAN_F0R2_FB29_Pos (29U)
4034 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4035 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4036 #define CAN_F0R2_FB30_Pos (30U)
4037 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4038 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4039 #define CAN_F0R2_FB31_Pos (31U)
4040 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4041 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4043 /******************* Bit definition for CAN_F1R2 register *******************/
4044 #define CAN_F1R2_FB0_Pos (0U)
4045 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4046 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4047 #define CAN_F1R2_FB1_Pos (1U)
4048 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4049 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4050 #define CAN_F1R2_FB2_Pos (2U)
4051 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4052 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4053 #define CAN_F1R2_FB3_Pos (3U)
4054 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4055 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4056 #define CAN_F1R2_FB4_Pos (4U)
4057 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4058 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4059 #define CAN_F1R2_FB5_Pos (5U)
4060 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4061 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4062 #define CAN_F1R2_FB6_Pos (6U)
4063 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4064 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4065 #define CAN_F1R2_FB7_Pos (7U)
4066 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4067 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4068 #define CAN_F1R2_FB8_Pos (8U)
4069 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4070 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4071 #define CAN_F1R2_FB9_Pos (9U)
4072 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4073 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4074 #define CAN_F1R2_FB10_Pos (10U)
4075 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4076 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4077 #define CAN_F1R2_FB11_Pos (11U)
4078 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4079 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4080 #define CAN_F1R2_FB12_Pos (12U)
4081 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4082 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4083 #define CAN_F1R2_FB13_Pos (13U)
4084 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4085 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4086 #define CAN_F1R2_FB14_Pos (14U)
4087 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4088 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4089 #define CAN_F1R2_FB15_Pos (15U)
4090 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4091 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4092 #define CAN_F1R2_FB16_Pos (16U)
4093 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4094 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4095 #define CAN_F1R2_FB17_Pos (17U)
4096 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4097 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4098 #define CAN_F1R2_FB18_Pos (18U)
4099 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4100 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4101 #define CAN_F1R2_FB19_Pos (19U)
4102 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4103 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4104 #define CAN_F1R2_FB20_Pos (20U)
4105 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4106 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4107 #define CAN_F1R2_FB21_Pos (21U)
4108 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4109 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4110 #define CAN_F1R2_FB22_Pos (22U)
4111 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4112 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4113 #define CAN_F1R2_FB23_Pos (23U)
4114 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4115 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4116 #define CAN_F1R2_FB24_Pos (24U)
4117 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4118 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4119 #define CAN_F1R2_FB25_Pos (25U)
4120 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4121 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4122 #define CAN_F1R2_FB26_Pos (26U)
4123 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4124 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4125 #define CAN_F1R2_FB27_Pos (27U)
4126 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4127 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4128 #define CAN_F1R2_FB28_Pos (28U)
4129 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4130 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4131 #define CAN_F1R2_FB29_Pos (29U)
4132 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4133 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4134 #define CAN_F1R2_FB30_Pos (30U)
4135 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4136 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4137 #define CAN_F1R2_FB31_Pos (31U)
4138 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4139 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4141 /******************* Bit definition for CAN_F2R2 register *******************/
4142 #define CAN_F2R2_FB0_Pos (0U)
4143 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4144 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4145 #define CAN_F2R2_FB1_Pos (1U)
4146 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4147 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4148 #define CAN_F2R2_FB2_Pos (2U)
4149 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4150 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4151 #define CAN_F2R2_FB3_Pos (3U)
4152 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4153 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4154 #define CAN_F2R2_FB4_Pos (4U)
4155 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4156 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4157 #define CAN_F2R2_FB5_Pos (5U)
4158 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4159 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4160 #define CAN_F2R2_FB6_Pos (6U)
4161 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4162 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4163 #define CAN_F2R2_FB7_Pos (7U)
4164 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4165 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4166 #define CAN_F2R2_FB8_Pos (8U)
4167 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4168 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4169 #define CAN_F2R2_FB9_Pos (9U)
4170 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4171 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4172 #define CAN_F2R2_FB10_Pos (10U)
4173 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4174 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4175 #define CAN_F2R2_FB11_Pos (11U)
4176 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4177 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4178 #define CAN_F2R2_FB12_Pos (12U)
4179 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4180 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4181 #define CAN_F2R2_FB13_Pos (13U)
4182 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4183 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4184 #define CAN_F2R2_FB14_Pos (14U)
4185 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4186 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4187 #define CAN_F2R2_FB15_Pos (15U)
4188 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4189 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4190 #define CAN_F2R2_FB16_Pos (16U)
4191 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4192 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4193 #define CAN_F2R2_FB17_Pos (17U)
4194 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4195 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4196 #define CAN_F2R2_FB18_Pos (18U)
4197 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4198 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4199 #define CAN_F2R2_FB19_Pos (19U)
4200 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4201 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4202 #define CAN_F2R2_FB20_Pos (20U)
4203 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4204 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4205 #define CAN_F2R2_FB21_Pos (21U)
4206 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4207 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4208 #define CAN_F2R2_FB22_Pos (22U)
4209 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4210 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4211 #define CAN_F2R2_FB23_Pos (23U)
4212 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4213 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4214 #define CAN_F2R2_FB24_Pos (24U)
4215 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4216 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4217 #define CAN_F2R2_FB25_Pos (25U)
4218 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4219 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4220 #define CAN_F2R2_FB26_Pos (26U)
4221 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4222 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4223 #define CAN_F2R2_FB27_Pos (27U)
4224 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4225 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4226 #define CAN_F2R2_FB28_Pos (28U)
4227 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4228 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4229 #define CAN_F2R2_FB29_Pos (29U)
4230 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4231 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4232 #define CAN_F2R2_FB30_Pos (30U)
4233 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4234 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4235 #define CAN_F2R2_FB31_Pos (31U)
4236 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4237 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4239 /******************* Bit definition for CAN_F3R2 register *******************/
4240 #define CAN_F3R2_FB0_Pos (0U)
4241 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4242 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4243 #define CAN_F3R2_FB1_Pos (1U)
4244 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4245 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4246 #define CAN_F3R2_FB2_Pos (2U)
4247 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4248 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4249 #define CAN_F3R2_FB3_Pos (3U)
4250 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4251 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4252 #define CAN_F3R2_FB4_Pos (4U)
4253 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4254 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4255 #define CAN_F3R2_FB5_Pos (5U)
4256 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4257 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4258 #define CAN_F3R2_FB6_Pos (6U)
4259 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4260 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4261 #define CAN_F3R2_FB7_Pos (7U)
4262 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4263 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4264 #define CAN_F3R2_FB8_Pos (8U)
4265 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4266 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4267 #define CAN_F3R2_FB9_Pos (9U)
4268 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4269 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4270 #define CAN_F3R2_FB10_Pos (10U)
4271 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4272 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4273 #define CAN_F3R2_FB11_Pos (11U)
4274 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4275 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4276 #define CAN_F3R2_FB12_Pos (12U)
4277 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4278 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4279 #define CAN_F3R2_FB13_Pos (13U)
4280 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4281 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4282 #define CAN_F3R2_FB14_Pos (14U)
4283 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4284 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4285 #define CAN_F3R2_FB15_Pos (15U)
4286 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4287 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4288 #define CAN_F3R2_FB16_Pos (16U)
4289 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4290 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4291 #define CAN_F3R2_FB17_Pos (17U)
4292 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4293 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4294 #define CAN_F3R2_FB18_Pos (18U)
4295 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4296 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4297 #define CAN_F3R2_FB19_Pos (19U)
4298 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4299 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4300 #define CAN_F3R2_FB20_Pos (20U)
4301 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4302 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4303 #define CAN_F3R2_FB21_Pos (21U)
4304 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4305 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4306 #define CAN_F3R2_FB22_Pos (22U)
4307 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4308 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4309 #define CAN_F3R2_FB23_Pos (23U)
4310 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4311 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4312 #define CAN_F3R2_FB24_Pos (24U)
4313 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4314 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4315 #define CAN_F3R2_FB25_Pos (25U)
4316 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4317 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4318 #define CAN_F3R2_FB26_Pos (26U)
4319 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4320 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4321 #define CAN_F3R2_FB27_Pos (27U)
4322 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4323 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4324 #define CAN_F3R2_FB28_Pos (28U)
4325 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4326 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4327 #define CAN_F3R2_FB29_Pos (29U)
4328 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4329 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4330 #define CAN_F3R2_FB30_Pos (30U)
4331 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4332 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4333 #define CAN_F3R2_FB31_Pos (31U)
4334 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4335 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4337 /******************* Bit definition for CAN_F4R2 register *******************/
4338 #define CAN_F4R2_FB0_Pos (0U)
4339 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4340 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4341 #define CAN_F4R2_FB1_Pos (1U)
4342 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4343 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4344 #define CAN_F4R2_FB2_Pos (2U)
4345 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4346 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4347 #define CAN_F4R2_FB3_Pos (3U)
4348 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4349 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4350 #define CAN_F4R2_FB4_Pos (4U)
4351 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4352 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4353 #define CAN_F4R2_FB5_Pos (5U)
4354 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4355 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4356 #define CAN_F4R2_FB6_Pos (6U)
4357 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4358 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4359 #define CAN_F4R2_FB7_Pos (7U)
4360 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4361 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4362 #define CAN_F4R2_FB8_Pos (8U)
4363 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4364 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4365 #define CAN_F4R2_FB9_Pos (9U)
4366 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4367 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4368 #define CAN_F4R2_FB10_Pos (10U)
4369 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4370 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4371 #define CAN_F4R2_FB11_Pos (11U)
4372 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4373 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4374 #define CAN_F4R2_FB12_Pos (12U)
4375 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4376 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4377 #define CAN_F4R2_FB13_Pos (13U)
4378 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4379 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4380 #define CAN_F4R2_FB14_Pos (14U)
4381 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4382 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4383 #define CAN_F4R2_FB15_Pos (15U)
4384 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4385 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4386 #define CAN_F4R2_FB16_Pos (16U)
4387 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4388 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4389 #define CAN_F4R2_FB17_Pos (17U)
4390 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4391 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4392 #define CAN_F4R2_FB18_Pos (18U)
4393 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4394 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4395 #define CAN_F4R2_FB19_Pos (19U)
4396 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4397 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4398 #define CAN_F4R2_FB20_Pos (20U)
4399 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4400 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4401 #define CAN_F4R2_FB21_Pos (21U)
4402 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4403 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4404 #define CAN_F4R2_FB22_Pos (22U)
4405 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4406 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4407 #define CAN_F4R2_FB23_Pos (23U)
4408 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4409 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4410 #define CAN_F4R2_FB24_Pos (24U)
4411 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4412 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4413 #define CAN_F4R2_FB25_Pos (25U)
4414 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4415 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4416 #define CAN_F4R2_FB26_Pos (26U)
4417 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4418 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4419 #define CAN_F4R2_FB27_Pos (27U)
4420 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4421 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4422 #define CAN_F4R2_FB28_Pos (28U)
4423 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4424 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4425 #define CAN_F4R2_FB29_Pos (29U)
4426 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4427 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4428 #define CAN_F4R2_FB30_Pos (30U)
4429 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4430 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4431 #define CAN_F4R2_FB31_Pos (31U)
4432 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4433 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4435 /******************* Bit definition for CAN_F5R2 register *******************/
4436 #define CAN_F5R2_FB0_Pos (0U)
4437 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4438 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4439 #define CAN_F5R2_FB1_Pos (1U)
4440 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4441 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4442 #define CAN_F5R2_FB2_Pos (2U)
4443 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4444 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4445 #define CAN_F5R2_FB3_Pos (3U)
4446 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4447 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4448 #define CAN_F5R2_FB4_Pos (4U)
4449 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4450 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4451 #define CAN_F5R2_FB5_Pos (5U)
4452 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4453 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4454 #define CAN_F5R2_FB6_Pos (6U)
4455 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4456 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4457 #define CAN_F5R2_FB7_Pos (7U)
4458 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4459 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4460 #define CAN_F5R2_FB8_Pos (8U)
4461 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4462 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4463 #define CAN_F5R2_FB9_Pos (9U)
4464 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4465 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4466 #define CAN_F5R2_FB10_Pos (10U)
4467 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4468 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4469 #define CAN_F5R2_FB11_Pos (11U)
4470 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4471 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4472 #define CAN_F5R2_FB12_Pos (12U)
4473 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4474 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4475 #define CAN_F5R2_FB13_Pos (13U)
4476 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4477 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4478 #define CAN_F5R2_FB14_Pos (14U)
4479 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4480 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4481 #define CAN_F5R2_FB15_Pos (15U)
4482 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4483 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4484 #define CAN_F5R2_FB16_Pos (16U)
4485 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4486 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4487 #define CAN_F5R2_FB17_Pos (17U)
4488 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4489 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4490 #define CAN_F5R2_FB18_Pos (18U)
4491 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4492 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4493 #define CAN_F5R2_FB19_Pos (19U)
4494 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4495 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4496 #define CAN_F5R2_FB20_Pos (20U)
4497 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4498 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4499 #define CAN_F5R2_FB21_Pos (21U)
4500 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4501 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4502 #define CAN_F5R2_FB22_Pos (22U)
4503 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4504 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4505 #define CAN_F5R2_FB23_Pos (23U)
4506 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4507 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4508 #define CAN_F5R2_FB24_Pos (24U)
4509 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4510 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4511 #define CAN_F5R2_FB25_Pos (25U)
4512 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4513 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4514 #define CAN_F5R2_FB26_Pos (26U)
4515 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4516 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4517 #define CAN_F5R2_FB27_Pos (27U)
4518 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4519 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4520 #define CAN_F5R2_FB28_Pos (28U)
4521 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4522 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4523 #define CAN_F5R2_FB29_Pos (29U)
4524 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4525 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4526 #define CAN_F5R2_FB30_Pos (30U)
4527 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4528 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4529 #define CAN_F5R2_FB31_Pos (31U)
4530 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4531 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4533 /******************* Bit definition for CAN_F6R2 register *******************/
4534 #define CAN_F6R2_FB0_Pos (0U)
4535 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4536 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4537 #define CAN_F6R2_FB1_Pos (1U)
4538 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4539 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4540 #define CAN_F6R2_FB2_Pos (2U)
4541 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4542 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4543 #define CAN_F6R2_FB3_Pos (3U)
4544 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4545 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4546 #define CAN_F6R2_FB4_Pos (4U)
4547 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4548 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4549 #define CAN_F6R2_FB5_Pos (5U)
4550 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4551 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4552 #define CAN_F6R2_FB6_Pos (6U)
4553 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4554 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4555 #define CAN_F6R2_FB7_Pos (7U)
4556 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4557 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4558 #define CAN_F6R2_FB8_Pos (8U)
4559 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4560 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4561 #define CAN_F6R2_FB9_Pos (9U)
4562 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4563 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4564 #define CAN_F6R2_FB10_Pos (10U)
4565 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4566 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4567 #define CAN_F6R2_FB11_Pos (11U)
4568 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4569 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4570 #define CAN_F6R2_FB12_Pos (12U)
4571 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4572 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4573 #define CAN_F6R2_FB13_Pos (13U)
4574 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4575 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4576 #define CAN_F6R2_FB14_Pos (14U)
4577 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4578 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4579 #define CAN_F6R2_FB15_Pos (15U)
4580 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4581 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4582 #define CAN_F6R2_FB16_Pos (16U)
4583 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4584 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4585 #define CAN_F6R2_FB17_Pos (17U)
4586 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4587 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4588 #define CAN_F6R2_FB18_Pos (18U)
4589 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4590 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4591 #define CAN_F6R2_FB19_Pos (19U)
4592 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4593 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4594 #define CAN_F6R2_FB20_Pos (20U)
4595 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4596 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4597 #define CAN_F6R2_FB21_Pos (21U)
4598 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4599 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4600 #define CAN_F6R2_FB22_Pos (22U)
4601 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4602 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4603 #define CAN_F6R2_FB23_Pos (23U)
4604 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4605 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4606 #define CAN_F6R2_FB24_Pos (24U)
4607 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4608 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4609 #define CAN_F6R2_FB25_Pos (25U)
4610 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4611 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4612 #define CAN_F6R2_FB26_Pos (26U)
4613 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4614 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4615 #define CAN_F6R2_FB27_Pos (27U)
4616 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4617 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4618 #define CAN_F6R2_FB28_Pos (28U)
4619 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4620 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4621 #define CAN_F6R2_FB29_Pos (29U)
4622 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4623 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4624 #define CAN_F6R2_FB30_Pos (30U)
4625 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4626 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4627 #define CAN_F6R2_FB31_Pos (31U)
4628 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4629 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4631 /******************* Bit definition for CAN_F7R2 register *******************/
4632 #define CAN_F7R2_FB0_Pos (0U)
4633 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4634 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4635 #define CAN_F7R2_FB1_Pos (1U)
4636 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4637 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4638 #define CAN_F7R2_FB2_Pos (2U)
4639 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4640 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4641 #define CAN_F7R2_FB3_Pos (3U)
4642 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4643 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4644 #define CAN_F7R2_FB4_Pos (4U)
4645 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4646 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4647 #define CAN_F7R2_FB5_Pos (5U)
4648 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4649 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4650 #define CAN_F7R2_FB6_Pos (6U)
4651 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4652 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4653 #define CAN_F7R2_FB7_Pos (7U)
4654 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4655 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4656 #define CAN_F7R2_FB8_Pos (8U)
4657 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4658 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4659 #define CAN_F7R2_FB9_Pos (9U)
4660 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4661 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4662 #define CAN_F7R2_FB10_Pos (10U)
4663 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4664 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4665 #define CAN_F7R2_FB11_Pos (11U)
4666 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4667 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4668 #define CAN_F7R2_FB12_Pos (12U)
4669 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4670 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4671 #define CAN_F7R2_FB13_Pos (13U)
4672 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4673 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4674 #define CAN_F7R2_FB14_Pos (14U)
4675 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4676 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4677 #define CAN_F7R2_FB15_Pos (15U)
4678 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4679 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4680 #define CAN_F7R2_FB16_Pos (16U)
4681 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4682 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4683 #define CAN_F7R2_FB17_Pos (17U)
4684 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4685 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4686 #define CAN_F7R2_FB18_Pos (18U)
4687 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4688 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4689 #define CAN_F7R2_FB19_Pos (19U)
4690 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4691 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4692 #define CAN_F7R2_FB20_Pos (20U)
4693 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4694 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4695 #define CAN_F7R2_FB21_Pos (21U)
4696 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4697 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4698 #define CAN_F7R2_FB22_Pos (22U)
4699 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4700 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4701 #define CAN_F7R2_FB23_Pos (23U)
4702 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4703 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4704 #define CAN_F7R2_FB24_Pos (24U)
4705 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4706 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4707 #define CAN_F7R2_FB25_Pos (25U)
4708 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4709 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4710 #define CAN_F7R2_FB26_Pos (26U)
4711 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4712 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4713 #define CAN_F7R2_FB27_Pos (27U)
4714 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4715 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4716 #define CAN_F7R2_FB28_Pos (28U)
4717 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4718 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4719 #define CAN_F7R2_FB29_Pos (29U)
4720 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4721 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4722 #define CAN_F7R2_FB30_Pos (30U)
4723 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4724 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4725 #define CAN_F7R2_FB31_Pos (31U)
4726 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4727 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4729 /******************* Bit definition for CAN_F8R2 register *******************/
4730 #define CAN_F8R2_FB0_Pos (0U)
4731 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4732 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4733 #define CAN_F8R2_FB1_Pos (1U)
4734 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4735 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4736 #define CAN_F8R2_FB2_Pos (2U)
4737 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4738 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4739 #define CAN_F8R2_FB3_Pos (3U)
4740 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4741 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4742 #define CAN_F8R2_FB4_Pos (4U)
4743 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4744 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4745 #define CAN_F8R2_FB5_Pos (5U)
4746 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4747 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4748 #define CAN_F8R2_FB6_Pos (6U)
4749 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4750 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4751 #define CAN_F8R2_FB7_Pos (7U)
4752 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4753 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4754 #define CAN_F8R2_FB8_Pos (8U)
4755 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4756 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4757 #define CAN_F8R2_FB9_Pos (9U)
4758 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4759 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4760 #define CAN_F8R2_FB10_Pos (10U)
4761 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4762 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4763 #define CAN_F8R2_FB11_Pos (11U)
4764 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4765 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4766 #define CAN_F8R2_FB12_Pos (12U)
4767 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4768 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4769 #define CAN_F8R2_FB13_Pos (13U)
4770 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4771 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4772 #define CAN_F8R2_FB14_Pos (14U)
4773 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4774 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4775 #define CAN_F8R2_FB15_Pos (15U)
4776 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4777 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4778 #define CAN_F8R2_FB16_Pos (16U)
4779 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4780 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4781 #define CAN_F8R2_FB17_Pos (17U)
4782 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4783 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4784 #define CAN_F8R2_FB18_Pos (18U)
4785 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4786 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4787 #define CAN_F8R2_FB19_Pos (19U)
4788 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4789 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4790 #define CAN_F8R2_FB20_Pos (20U)
4791 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4792 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4793 #define CAN_F8R2_FB21_Pos (21U)
4794 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4795 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4796 #define CAN_F8R2_FB22_Pos (22U)
4797 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4798 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4799 #define CAN_F8R2_FB23_Pos (23U)
4800 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4801 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4802 #define CAN_F8R2_FB24_Pos (24U)
4803 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4804 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4805 #define CAN_F8R2_FB25_Pos (25U)
4806 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4807 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4808 #define CAN_F8R2_FB26_Pos (26U)
4809 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4810 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4811 #define CAN_F8R2_FB27_Pos (27U)
4812 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4813 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4814 #define CAN_F8R2_FB28_Pos (28U)
4815 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4816 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4817 #define CAN_F8R2_FB29_Pos (29U)
4818 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4819 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4820 #define CAN_F8R2_FB30_Pos (30U)
4821 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4822 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4823 #define CAN_F8R2_FB31_Pos (31U)
4824 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4825 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4827 /******************* Bit definition for CAN_F9R2 register *******************/
4828 #define CAN_F9R2_FB0_Pos (0U)
4829 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4830 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4831 #define CAN_F9R2_FB1_Pos (1U)
4832 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4833 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4834 #define CAN_F9R2_FB2_Pos (2U)
4835 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4836 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4837 #define CAN_F9R2_FB3_Pos (3U)
4838 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4839 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4840 #define CAN_F9R2_FB4_Pos (4U)
4841 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4842 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4843 #define CAN_F9R2_FB5_Pos (5U)
4844 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4845 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4846 #define CAN_F9R2_FB6_Pos (6U)
4847 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4848 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4849 #define CAN_F9R2_FB7_Pos (7U)
4850 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4851 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4852 #define CAN_F9R2_FB8_Pos (8U)
4853 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4854 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4855 #define CAN_F9R2_FB9_Pos (9U)
4856 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4857 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4858 #define CAN_F9R2_FB10_Pos (10U)
4859 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4860 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4861 #define CAN_F9R2_FB11_Pos (11U)
4862 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4863 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4864 #define CAN_F9R2_FB12_Pos (12U)
4865 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4866 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4867 #define CAN_F9R2_FB13_Pos (13U)
4868 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4869 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4870 #define CAN_F9R2_FB14_Pos (14U)
4871 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4872 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4873 #define CAN_F9R2_FB15_Pos (15U)
4874 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4875 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4876 #define CAN_F9R2_FB16_Pos (16U)
4877 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4878 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4879 #define CAN_F9R2_FB17_Pos (17U)
4880 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4881 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4882 #define CAN_F9R2_FB18_Pos (18U)
4883 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4884 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4885 #define CAN_F9R2_FB19_Pos (19U)
4886 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4887 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4888 #define CAN_F9R2_FB20_Pos (20U)
4889 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
4890 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
4891 #define CAN_F9R2_FB21_Pos (21U)
4892 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
4893 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
4894 #define CAN_F9R2_FB22_Pos (22U)
4895 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
4896 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
4897 #define CAN_F9R2_FB23_Pos (23U)
4898 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
4899 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
4900 #define CAN_F9R2_FB24_Pos (24U)
4901 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
4902 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
4903 #define CAN_F9R2_FB25_Pos (25U)
4904 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
4905 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
4906 #define CAN_F9R2_FB26_Pos (26U)
4907 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
4908 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
4909 #define CAN_F9R2_FB27_Pos (27U)
4910 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
4911 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
4912 #define CAN_F9R2_FB28_Pos (28U)
4913 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
4914 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
4915 #define CAN_F9R2_FB29_Pos (29U)
4916 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
4917 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
4918 #define CAN_F9R2_FB30_Pos (30U)
4919 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
4920 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
4921 #define CAN_F9R2_FB31_Pos (31U)
4922 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
4923 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
4925 /******************* Bit definition for CAN_F10R2 register ******************/
4926 #define CAN_F10R2_FB0_Pos (0U)
4927 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
4928 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
4929 #define CAN_F10R2_FB1_Pos (1U)
4930 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
4931 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
4932 #define CAN_F10R2_FB2_Pos (2U)
4933 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
4934 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
4935 #define CAN_F10R2_FB3_Pos (3U)
4936 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
4937 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
4938 #define CAN_F10R2_FB4_Pos (4U)
4939 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
4940 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
4941 #define CAN_F10R2_FB5_Pos (5U)
4942 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
4943 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
4944 #define CAN_F10R2_FB6_Pos (6U)
4945 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
4946 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
4947 #define CAN_F10R2_FB7_Pos (7U)
4948 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
4949 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
4950 #define CAN_F10R2_FB8_Pos (8U)
4951 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
4952 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
4953 #define CAN_F10R2_FB9_Pos (9U)
4954 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
4955 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
4956 #define CAN_F10R2_FB10_Pos (10U)
4957 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
4958 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
4959 #define CAN_F10R2_FB11_Pos (11U)
4960 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
4961 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
4962 #define CAN_F10R2_FB12_Pos (12U)
4963 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
4964 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
4965 #define CAN_F10R2_FB13_Pos (13U)
4966 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
4967 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
4968 #define CAN_F10R2_FB14_Pos (14U)
4969 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
4970 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
4971 #define CAN_F10R2_FB15_Pos (15U)
4972 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
4973 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
4974 #define CAN_F10R2_FB16_Pos (16U)
4975 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
4976 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
4977 #define CAN_F10R2_FB17_Pos (17U)
4978 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
4979 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
4980 #define CAN_F10R2_FB18_Pos (18U)
4981 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
4982 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
4983 #define CAN_F10R2_FB19_Pos (19U)
4984 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
4985 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
4986 #define CAN_F10R2_FB20_Pos (20U)
4987 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
4988 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
4989 #define CAN_F10R2_FB21_Pos (21U)
4990 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
4991 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
4992 #define CAN_F10R2_FB22_Pos (22U)
4993 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
4994 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
4995 #define CAN_F10R2_FB23_Pos (23U)
4996 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
4997 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
4998 #define CAN_F10R2_FB24_Pos (24U)
4999 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5000 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5001 #define CAN_F10R2_FB25_Pos (25U)
5002 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5003 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5004 #define CAN_F10R2_FB26_Pos (26U)
5005 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5006 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5007 #define CAN_F10R2_FB27_Pos (27U)
5008 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5009 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5010 #define CAN_F10R2_FB28_Pos (28U)
5011 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5012 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5013 #define CAN_F10R2_FB29_Pos (29U)
5014 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5015 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5016 #define CAN_F10R2_FB30_Pos (30U)
5017 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5018 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5019 #define CAN_F10R2_FB31_Pos (31U)
5020 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5021 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5023 /******************* Bit definition for CAN_F11R2 register ******************/
5024 #define CAN_F11R2_FB0_Pos (0U)
5025 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5026 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5027 #define CAN_F11R2_FB1_Pos (1U)
5028 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5029 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5030 #define CAN_F11R2_FB2_Pos (2U)
5031 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5032 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5033 #define CAN_F11R2_FB3_Pos (3U)
5034 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5035 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5036 #define CAN_F11R2_FB4_Pos (4U)
5037 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5038 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5039 #define CAN_F11R2_FB5_Pos (5U)
5040 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5041 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5042 #define CAN_F11R2_FB6_Pos (6U)
5043 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5044 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5045 #define CAN_F11R2_FB7_Pos (7U)
5046 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5047 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5048 #define CAN_F11R2_FB8_Pos (8U)
5049 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5050 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5051 #define CAN_F11R2_FB9_Pos (9U)
5052 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5053 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5054 #define CAN_F11R2_FB10_Pos (10U)
5055 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5056 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5057 #define CAN_F11R2_FB11_Pos (11U)
5058 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5059 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5060 #define CAN_F11R2_FB12_Pos (12U)
5061 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5062 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5063 #define CAN_F11R2_FB13_Pos (13U)
5064 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5065 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5066 #define CAN_F11R2_FB14_Pos (14U)
5067 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5068 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5069 #define CAN_F11R2_FB15_Pos (15U)
5070 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5071 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5072 #define CAN_F11R2_FB16_Pos (16U)
5073 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5074 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5075 #define CAN_F11R2_FB17_Pos (17U)
5076 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5077 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5078 #define CAN_F11R2_FB18_Pos (18U)
5079 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5080 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5081 #define CAN_F11R2_FB19_Pos (19U)
5082 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5083 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5084 #define CAN_F11R2_FB20_Pos (20U)
5085 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5086 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5087 #define CAN_F11R2_FB21_Pos (21U)
5088 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5089 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5090 #define CAN_F11R2_FB22_Pos (22U)
5091 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5092 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5093 #define CAN_F11R2_FB23_Pos (23U)
5094 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5095 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5096 #define CAN_F11R2_FB24_Pos (24U)
5097 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5098 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5099 #define CAN_F11R2_FB25_Pos (25U)
5100 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5101 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5102 #define CAN_F11R2_FB26_Pos (26U)
5103 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5104 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5105 #define CAN_F11R2_FB27_Pos (27U)
5106 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5107 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5108 #define CAN_F11R2_FB28_Pos (28U)
5109 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5110 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5111 #define CAN_F11R2_FB29_Pos (29U)
5112 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5113 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5114 #define CAN_F11R2_FB30_Pos (30U)
5115 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5116 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5117 #define CAN_F11R2_FB31_Pos (31U)
5118 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5119 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5121 /******************* Bit definition for CAN_F12R2 register ******************/
5122 #define CAN_F12R2_FB0_Pos (0U)
5123 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5124 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5125 #define CAN_F12R2_FB1_Pos (1U)
5126 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5127 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5128 #define CAN_F12R2_FB2_Pos (2U)
5129 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5130 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5131 #define CAN_F12R2_FB3_Pos (3U)
5132 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5133 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5134 #define CAN_F12R2_FB4_Pos (4U)
5135 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5136 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5137 #define CAN_F12R2_FB5_Pos (5U)
5138 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5139 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5140 #define CAN_F12R2_FB6_Pos (6U)
5141 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5142 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5143 #define CAN_F12R2_FB7_Pos (7U)
5144 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5145 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5146 #define CAN_F12R2_FB8_Pos (8U)
5147 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5148 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5149 #define CAN_F12R2_FB9_Pos (9U)
5150 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5151 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5152 #define CAN_F12R2_FB10_Pos (10U)
5153 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5154 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5155 #define CAN_F12R2_FB11_Pos (11U)
5156 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5157 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5158 #define CAN_F12R2_FB12_Pos (12U)
5159 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5160 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5161 #define CAN_F12R2_FB13_Pos (13U)
5162 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5163 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5164 #define CAN_F12R2_FB14_Pos (14U)
5165 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5166 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5167 #define CAN_F12R2_FB15_Pos (15U)
5168 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5169 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5170 #define CAN_F12R2_FB16_Pos (16U)
5171 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5172 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5173 #define CAN_F12R2_FB17_Pos (17U)
5174 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5175 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5176 #define CAN_F12R2_FB18_Pos (18U)
5177 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5178 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5179 #define CAN_F12R2_FB19_Pos (19U)
5180 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5181 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5182 #define CAN_F12R2_FB20_Pos (20U)
5183 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5184 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5185 #define CAN_F12R2_FB21_Pos (21U)
5186 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5187 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5188 #define CAN_F12R2_FB22_Pos (22U)
5189 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5190 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5191 #define CAN_F12R2_FB23_Pos (23U)
5192 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5193 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5194 #define CAN_F12R2_FB24_Pos (24U)
5195 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5196 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5197 #define CAN_F12R2_FB25_Pos (25U)
5198 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5199 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5200 #define CAN_F12R2_FB26_Pos (26U)
5201 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5202 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5203 #define CAN_F12R2_FB27_Pos (27U)
5204 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5205 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5206 #define CAN_F12R2_FB28_Pos (28U)
5207 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5208 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5209 #define CAN_F12R2_FB29_Pos (29U)
5210 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5211 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5212 #define CAN_F12R2_FB30_Pos (30U)
5213 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5214 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5215 #define CAN_F12R2_FB31_Pos (31U)
5216 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5217 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5219 /******************* Bit definition for CAN_F13R2 register ******************/
5220 #define CAN_F13R2_FB0_Pos (0U)
5221 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5222 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5223 #define CAN_F13R2_FB1_Pos (1U)
5224 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5225 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5226 #define CAN_F13R2_FB2_Pos (2U)
5227 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5228 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5229 #define CAN_F13R2_FB3_Pos (3U)
5230 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5231 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5232 #define CAN_F13R2_FB4_Pos (4U)
5233 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5234 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5235 #define CAN_F13R2_FB5_Pos (5U)
5236 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5237 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5238 #define CAN_F13R2_FB6_Pos (6U)
5239 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5240 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5241 #define CAN_F13R2_FB7_Pos (7U)
5242 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5243 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5244 #define CAN_F13R2_FB8_Pos (8U)
5245 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5246 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5247 #define CAN_F13R2_FB9_Pos (9U)
5248 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5249 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5250 #define CAN_F13R2_FB10_Pos (10U)
5251 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5252 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5253 #define CAN_F13R2_FB11_Pos (11U)
5254 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5255 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5256 #define CAN_F13R2_FB12_Pos (12U)
5257 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5258 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5259 #define CAN_F13R2_FB13_Pos (13U)
5260 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5261 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5262 #define CAN_F13R2_FB14_Pos (14U)
5263 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5264 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5265 #define CAN_F13R2_FB15_Pos (15U)
5266 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5267 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5268 #define CAN_F13R2_FB16_Pos (16U)
5269 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5270 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5271 #define CAN_F13R2_FB17_Pos (17U)
5272 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5273 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5274 #define CAN_F13R2_FB18_Pos (18U)
5275 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5276 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5277 #define CAN_F13R2_FB19_Pos (19U)
5278 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5279 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5280 #define CAN_F13R2_FB20_Pos (20U)
5281 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5282 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5283 #define CAN_F13R2_FB21_Pos (21U)
5284 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5285 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5286 #define CAN_F13R2_FB22_Pos (22U)
5287 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5288 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5289 #define CAN_F13R2_FB23_Pos (23U)
5290 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5291 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5292 #define CAN_F13R2_FB24_Pos (24U)
5293 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5294 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5295 #define CAN_F13R2_FB25_Pos (25U)
5296 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5297 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5298 #define CAN_F13R2_FB26_Pos (26U)
5299 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5300 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5301 #define CAN_F13R2_FB27_Pos (27U)
5302 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5303 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5304 #define CAN_F13R2_FB28_Pos (28U)
5305 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5306 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5307 #define CAN_F13R2_FB29_Pos (29U)
5308 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5309 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5310 #define CAN_F13R2_FB30_Pos (30U)
5311 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5312 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5313 #define CAN_F13R2_FB31_Pos (31U)
5314 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5315 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5317 /******************************************************************************/
5318 /* */
5319 /* CRC calculation unit */
5320 /* */
5321 /******************************************************************************/
5322 /******************* Bit definition for CRC_DR register *********************/
5323 #define CRC_DR_DR_Pos (0U)
5324 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5325 #define CRC_DR_DR CRC_DR_DR_Msk
5328 /******************* Bit definition for CRC_IDR register ********************/
5329 #define CRC_IDR_IDR_Pos (0U)
5330 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5331 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
5334 /******************** Bit definition for CRC_CR register ********************/
5335 #define CRC_CR_RESET_Pos (0U)
5336 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5337 #define CRC_CR_RESET CRC_CR_RESET_Msk
5339 /******************************************************************************/
5340 /* */
5341 /* Digital to Analog Converter */
5342 /* */
5343 /******************************************************************************/
5344 /*
5345  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5346  */
5347 #define DAC_CHANNEL2_SUPPORT
5348 /******************** Bit definition for DAC_CR register ********************/
5349 #define DAC_CR_EN1_Pos (0U)
5350 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5351 #define DAC_CR_EN1 DAC_CR_EN1_Msk
5352 #define DAC_CR_BOFF1_Pos (1U)
5353 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5354 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5355 #define DAC_CR_TEN1_Pos (2U)
5356 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5357 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5359 #define DAC_CR_TSEL1_Pos (3U)
5360 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5361 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5362 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5363 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5364 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5366 #define DAC_CR_WAVE1_Pos (6U)
5367 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5368 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5369 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5370 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5372 #define DAC_CR_MAMP1_Pos (8U)
5373 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5374 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5375 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5376 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5377 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5378 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5380 #define DAC_CR_DMAEN1_Pos (12U)
5381 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5382 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5383 #define DAC_CR_DMAUDRIE1_Pos (13U)
5384 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5385 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5386 #define DAC_CR_EN2_Pos (16U)
5387 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5388 #define DAC_CR_EN2 DAC_CR_EN2_Msk
5389 #define DAC_CR_BOFF2_Pos (17U)
5390 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5391 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5392 #define DAC_CR_TEN2_Pos (18U)
5393 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5394 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5396 #define DAC_CR_TSEL2_Pos (19U)
5397 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5398 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5399 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5400 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5401 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5403 #define DAC_CR_WAVE2_Pos (22U)
5404 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5405 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5406 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5407 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5409 #define DAC_CR_MAMP2_Pos (24U)
5410 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5411 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5412 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5413 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5414 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5415 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5417 #define DAC_CR_DMAEN2_Pos (28U)
5418 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5419 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5420 #define DAC_CR_DMAUDRIE2_Pos (29U)
5421 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5422 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5424 /***************** Bit definition for DAC_SWTRIGR register ******************/
5425 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5426 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5427 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5428 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5429 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5430 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5432 /***************** Bit definition for DAC_DHR12R1 register ******************/
5433 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5434 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5435 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5437 /***************** Bit definition for DAC_DHR12L1 register ******************/
5438 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5439 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5440 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5442 /****************** Bit definition for DAC_DHR8R1 register ******************/
5443 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5444 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5445 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5447 /***************** Bit definition for DAC_DHR12R2 register ******************/
5448 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5449 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5450 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5452 /***************** Bit definition for DAC_DHR12L2 register ******************/
5453 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5454 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5455 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5457 /****************** Bit definition for DAC_DHR8R2 register ******************/
5458 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5459 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5460 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5462 /***************** Bit definition for DAC_DHR12RD register ******************/
5463 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5464 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5465 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5466 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5467 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5468 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5470 /***************** Bit definition for DAC_DHR12LD register ******************/
5471 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5472 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5473 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5474 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5475 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5476 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5478 /****************** Bit definition for DAC_DHR8RD register ******************/
5479 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5480 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5481 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5482 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5483 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5484 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5486 /******************* Bit definition for DAC_DOR1 register *******************/
5487 #define DAC_DOR1_DACC1DOR_Pos (0U)
5488 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5489 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5491 /******************* Bit definition for DAC_DOR2 register *******************/
5492 #define DAC_DOR2_DACC2DOR_Pos (0U)
5493 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5494 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5496 /******************** Bit definition for DAC_SR register ********************/
5497 #define DAC_SR_DMAUDR1_Pos (13U)
5498 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5499 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5500 #define DAC_SR_DMAUDR2_Pos (29U)
5501 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5502 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5505 /******************************************************************************/
5506 /* */
5507 /* DMA Controller */
5508 /* */
5509 /******************************************************************************/
5510 /******************** Bits definition for DMA_SxCR register *****************/
5511 #define DMA_SxCR_CHSEL_Pos (25U)
5512 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5513 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5514 #define DMA_SxCR_CHSEL_0 0x02000000U
5515 #define DMA_SxCR_CHSEL_1 0x04000000U
5516 #define DMA_SxCR_CHSEL_2 0x08000000U
5517 #define DMA_SxCR_MBURST_Pos (23U)
5518 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5519 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5520 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5521 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5522 #define DMA_SxCR_PBURST_Pos (21U)
5523 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5524 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5525 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5526 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5527 #define DMA_SxCR_CT_Pos (19U)
5528 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5529 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5530 #define DMA_SxCR_DBM_Pos (18U)
5531 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5532 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5533 #define DMA_SxCR_PL_Pos (16U)
5534 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5535 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
5536 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5537 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5538 #define DMA_SxCR_PINCOS_Pos (15U)
5539 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5540 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5541 #define DMA_SxCR_MSIZE_Pos (13U)
5542 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5543 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5544 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5545 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5546 #define DMA_SxCR_PSIZE_Pos (11U)
5547 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5548 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5549 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5550 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5551 #define DMA_SxCR_MINC_Pos (10U)
5552 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5553 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5554 #define DMA_SxCR_PINC_Pos (9U)
5555 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5556 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5557 #define DMA_SxCR_CIRC_Pos (8U)
5558 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5559 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5560 #define DMA_SxCR_DIR_Pos (6U)
5561 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5562 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5563 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5564 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5565 #define DMA_SxCR_PFCTRL_Pos (5U)
5566 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5567 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5568 #define DMA_SxCR_TCIE_Pos (4U)
5569 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5570 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5571 #define DMA_SxCR_HTIE_Pos (3U)
5572 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5573 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5574 #define DMA_SxCR_TEIE_Pos (2U)
5575 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5576 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5577 #define DMA_SxCR_DMEIE_Pos (1U)
5578 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5579 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5580 #define DMA_SxCR_EN_Pos (0U)
5581 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
5582 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
5583 
5584 /* Legacy defines */
5585 #define DMA_SxCR_ACK_Pos (20U)
5586 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
5587 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5588 
5589 /******************** Bits definition for DMA_SxCNDTR register **************/
5590 #define DMA_SxNDT_Pos (0U)
5591 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
5592 #define DMA_SxNDT DMA_SxNDT_Msk
5593 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
5594 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
5595 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
5596 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
5597 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
5598 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
5599 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
5600 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
5601 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
5602 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
5603 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
5604 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
5605 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
5606 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
5607 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
5608 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
5610 /******************** Bits definition for DMA_SxFCR register ****************/
5611 #define DMA_SxFCR_FEIE_Pos (7U)
5612 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
5613 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5614 #define DMA_SxFCR_FS_Pos (3U)
5615 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
5616 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5617 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
5618 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
5619 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
5620 #define DMA_SxFCR_DMDIS_Pos (2U)
5621 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
5622 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5623 #define DMA_SxFCR_FTH_Pos (0U)
5624 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
5625 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5626 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
5627 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
5629 /******************** Bits definition for DMA_LISR register *****************/
5630 #define DMA_LISR_TCIF3_Pos (27U)
5631 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
5632 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5633 #define DMA_LISR_HTIF3_Pos (26U)
5634 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
5635 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5636 #define DMA_LISR_TEIF3_Pos (25U)
5637 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
5638 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5639 #define DMA_LISR_DMEIF3_Pos (24U)
5640 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
5641 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5642 #define DMA_LISR_FEIF3_Pos (22U)
5643 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
5644 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5645 #define DMA_LISR_TCIF2_Pos (21U)
5646 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
5647 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5648 #define DMA_LISR_HTIF2_Pos (20U)
5649 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
5650 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5651 #define DMA_LISR_TEIF2_Pos (19U)
5652 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
5653 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5654 #define DMA_LISR_DMEIF2_Pos (18U)
5655 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
5656 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5657 #define DMA_LISR_FEIF2_Pos (16U)
5658 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
5659 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5660 #define DMA_LISR_TCIF1_Pos (11U)
5661 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
5662 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5663 #define DMA_LISR_HTIF1_Pos (10U)
5664 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
5665 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5666 #define DMA_LISR_TEIF1_Pos (9U)
5667 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
5668 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5669 #define DMA_LISR_DMEIF1_Pos (8U)
5670 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
5671 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5672 #define DMA_LISR_FEIF1_Pos (6U)
5673 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
5674 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5675 #define DMA_LISR_TCIF0_Pos (5U)
5676 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
5677 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5678 #define DMA_LISR_HTIF0_Pos (4U)
5679 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
5680 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5681 #define DMA_LISR_TEIF0_Pos (3U)
5682 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
5683 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5684 #define DMA_LISR_DMEIF0_Pos (2U)
5685 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
5686 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5687 #define DMA_LISR_FEIF0_Pos (0U)
5688 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
5689 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5690 
5691 /******************** Bits definition for DMA_HISR register *****************/
5692 #define DMA_HISR_TCIF7_Pos (27U)
5693 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
5694 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5695 #define DMA_HISR_HTIF7_Pos (26U)
5696 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
5697 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
5698 #define DMA_HISR_TEIF7_Pos (25U)
5699 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
5700 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
5701 #define DMA_HISR_DMEIF7_Pos (24U)
5702 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
5703 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
5704 #define DMA_HISR_FEIF7_Pos (22U)
5705 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
5706 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
5707 #define DMA_HISR_TCIF6_Pos (21U)
5708 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
5709 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
5710 #define DMA_HISR_HTIF6_Pos (20U)
5711 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
5712 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
5713 #define DMA_HISR_TEIF6_Pos (19U)
5714 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
5715 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
5716 #define DMA_HISR_DMEIF6_Pos (18U)
5717 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
5718 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
5719 #define DMA_HISR_FEIF6_Pos (16U)
5720 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
5721 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
5722 #define DMA_HISR_TCIF5_Pos (11U)
5723 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
5724 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
5725 #define DMA_HISR_HTIF5_Pos (10U)
5726 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
5727 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
5728 #define DMA_HISR_TEIF5_Pos (9U)
5729 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
5730 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
5731 #define DMA_HISR_DMEIF5_Pos (8U)
5732 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
5733 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
5734 #define DMA_HISR_FEIF5_Pos (6U)
5735 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
5736 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
5737 #define DMA_HISR_TCIF4_Pos (5U)
5738 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
5739 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
5740 #define DMA_HISR_HTIF4_Pos (4U)
5741 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
5742 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
5743 #define DMA_HISR_TEIF4_Pos (3U)
5744 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
5745 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
5746 #define DMA_HISR_DMEIF4_Pos (2U)
5747 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
5748 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
5749 #define DMA_HISR_FEIF4_Pos (0U)
5750 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
5751 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
5752 
5753 /******************** Bits definition for DMA_LIFCR register ****************/
5754 #define DMA_LIFCR_CTCIF3_Pos (27U)
5755 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
5756 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
5757 #define DMA_LIFCR_CHTIF3_Pos (26U)
5758 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
5759 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
5760 #define DMA_LIFCR_CTEIF3_Pos (25U)
5761 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
5762 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
5763 #define DMA_LIFCR_CDMEIF3_Pos (24U)
5764 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
5765 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
5766 #define DMA_LIFCR_CFEIF3_Pos (22U)
5767 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
5768 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
5769 #define DMA_LIFCR_CTCIF2_Pos (21U)
5770 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
5771 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
5772 #define DMA_LIFCR_CHTIF2_Pos (20U)
5773 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
5774 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
5775 #define DMA_LIFCR_CTEIF2_Pos (19U)
5776 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
5777 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
5778 #define DMA_LIFCR_CDMEIF2_Pos (18U)
5779 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
5780 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
5781 #define DMA_LIFCR_CFEIF2_Pos (16U)
5782 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
5783 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
5784 #define DMA_LIFCR_CTCIF1_Pos (11U)
5785 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
5786 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
5787 #define DMA_LIFCR_CHTIF1_Pos (10U)
5788 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
5789 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
5790 #define DMA_LIFCR_CTEIF1_Pos (9U)
5791 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
5792 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
5793 #define DMA_LIFCR_CDMEIF1_Pos (8U)
5794 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
5795 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
5796 #define DMA_LIFCR_CFEIF1_Pos (6U)
5797 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
5798 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
5799 #define DMA_LIFCR_CTCIF0_Pos (5U)
5800 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
5801 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
5802 #define DMA_LIFCR_CHTIF0_Pos (4U)
5803 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
5804 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
5805 #define DMA_LIFCR_CTEIF0_Pos (3U)
5806 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
5807 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
5808 #define DMA_LIFCR_CDMEIF0_Pos (2U)
5809 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
5810 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
5811 #define DMA_LIFCR_CFEIF0_Pos (0U)
5812 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
5813 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
5814 
5815 /******************** Bits definition for DMA_HIFCR register ****************/
5816 #define DMA_HIFCR_CTCIF7_Pos (27U)
5817 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
5818 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
5819 #define DMA_HIFCR_CHTIF7_Pos (26U)
5820 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
5821 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
5822 #define DMA_HIFCR_CTEIF7_Pos (25U)
5823 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
5824 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
5825 #define DMA_HIFCR_CDMEIF7_Pos (24U)
5826 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
5827 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
5828 #define DMA_HIFCR_CFEIF7_Pos (22U)
5829 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
5830 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
5831 #define DMA_HIFCR_CTCIF6_Pos (21U)
5832 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
5833 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
5834 #define DMA_HIFCR_CHTIF6_Pos (20U)
5835 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
5836 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
5837 #define DMA_HIFCR_CTEIF6_Pos (19U)
5838 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
5839 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
5840 #define DMA_HIFCR_CDMEIF6_Pos (18U)
5841 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
5842 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
5843 #define DMA_HIFCR_CFEIF6_Pos (16U)
5844 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
5845 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
5846 #define DMA_HIFCR_CTCIF5_Pos (11U)
5847 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
5848 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
5849 #define DMA_HIFCR_CHTIF5_Pos (10U)
5850 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
5851 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
5852 #define DMA_HIFCR_CTEIF5_Pos (9U)
5853 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
5854 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
5855 #define DMA_HIFCR_CDMEIF5_Pos (8U)
5856 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
5857 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
5858 #define DMA_HIFCR_CFEIF5_Pos (6U)
5859 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
5860 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
5861 #define DMA_HIFCR_CTCIF4_Pos (5U)
5862 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
5863 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
5864 #define DMA_HIFCR_CHTIF4_Pos (4U)
5865 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
5866 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
5867 #define DMA_HIFCR_CTEIF4_Pos (3U)
5868 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
5869 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
5870 #define DMA_HIFCR_CDMEIF4_Pos (2U)
5871 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
5872 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
5873 #define DMA_HIFCR_CFEIF4_Pos (0U)
5874 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
5875 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
5876 
5877 /****************** Bit definition for DMA_SxPAR register ********************/
5878 #define DMA_SxPAR_PA_Pos (0U)
5879 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
5880 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
5882 /****************** Bit definition for DMA_SxM0AR register ********************/
5883 #define DMA_SxM0AR_M0A_Pos (0U)
5884 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
5885 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
5887 /****************** Bit definition for DMA_SxM1AR register ********************/
5888 #define DMA_SxM1AR_M1A_Pos (0U)
5889 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
5890 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
5893 /******************************************************************************/
5894 /* */
5895 /* External Interrupt/Event Controller */
5896 /* */
5897 /******************************************************************************/
5898 /******************* Bit definition for EXTI_IMR register *******************/
5899 #define EXTI_IMR_MR0_Pos (0U)
5900 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
5901 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
5902 #define EXTI_IMR_MR1_Pos (1U)
5903 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
5904 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
5905 #define EXTI_IMR_MR2_Pos (2U)
5906 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
5907 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
5908 #define EXTI_IMR_MR3_Pos (3U)
5909 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
5910 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
5911 #define EXTI_IMR_MR4_Pos (4U)
5912 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
5913 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
5914 #define EXTI_IMR_MR5_Pos (5U)
5915 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
5916 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
5917 #define EXTI_IMR_MR6_Pos (6U)
5918 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
5919 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
5920 #define EXTI_IMR_MR7_Pos (7U)
5921 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
5922 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
5923 #define EXTI_IMR_MR8_Pos (8U)
5924 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
5925 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
5926 #define EXTI_IMR_MR9_Pos (9U)
5927 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
5928 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
5929 #define EXTI_IMR_MR10_Pos (10U)
5930 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
5931 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
5932 #define EXTI_IMR_MR11_Pos (11U)
5933 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
5934 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
5935 #define EXTI_IMR_MR12_Pos (12U)
5936 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
5937 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
5938 #define EXTI_IMR_MR13_Pos (13U)
5939 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
5940 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
5941 #define EXTI_IMR_MR14_Pos (14U)
5942 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
5943 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
5944 #define EXTI_IMR_MR15_Pos (15U)
5945 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
5946 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
5947 #define EXTI_IMR_MR16_Pos (16U)
5948 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
5949 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
5950 #define EXTI_IMR_MR17_Pos (17U)
5951 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
5952 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
5953 #define EXTI_IMR_MR18_Pos (18U)
5954 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
5955 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
5956 #define EXTI_IMR_MR19_Pos (19U)
5957 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
5958 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
5959 #define EXTI_IMR_MR20_Pos (20U)
5960 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
5961 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
5962 #define EXTI_IMR_MR21_Pos (21U)
5963 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
5964 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
5965 #define EXTI_IMR_MR22_Pos (22U)
5966 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
5967 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
5969 /* Reference Defines */
5970 #define EXTI_IMR_IM0 EXTI_IMR_MR0
5971 #define EXTI_IMR_IM1 EXTI_IMR_MR1
5972 #define EXTI_IMR_IM2 EXTI_IMR_MR2
5973 #define EXTI_IMR_IM3 EXTI_IMR_MR3
5974 #define EXTI_IMR_IM4 EXTI_IMR_MR4
5975 #define EXTI_IMR_IM5 EXTI_IMR_MR5
5976 #define EXTI_IMR_IM6 EXTI_IMR_MR6
5977 #define EXTI_IMR_IM7 EXTI_IMR_MR7
5978 #define EXTI_IMR_IM8 EXTI_IMR_MR8
5979 #define EXTI_IMR_IM9 EXTI_IMR_MR9
5980 #define EXTI_IMR_IM10 EXTI_IMR_MR10
5981 #define EXTI_IMR_IM11 EXTI_IMR_MR11
5982 #define EXTI_IMR_IM12 EXTI_IMR_MR12
5983 #define EXTI_IMR_IM13 EXTI_IMR_MR13
5984 #define EXTI_IMR_IM14 EXTI_IMR_MR14
5985 #define EXTI_IMR_IM15 EXTI_IMR_MR15
5986 #define EXTI_IMR_IM16 EXTI_IMR_MR16
5987 #define EXTI_IMR_IM17 EXTI_IMR_MR17
5988 #define EXTI_IMR_IM18 EXTI_IMR_MR18
5989 #define EXTI_IMR_IM19 EXTI_IMR_MR19
5990 #define EXTI_IMR_IM20 EXTI_IMR_MR20
5991 #define EXTI_IMR_IM21 EXTI_IMR_MR21
5992 #define EXTI_IMR_IM22 EXTI_IMR_MR22
5993 #define EXTI_IMR_IM_Pos (0U)
5994 #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
5995 #define EXTI_IMR_IM EXTI_IMR_IM_Msk
5997 /******************* Bit definition for EXTI_EMR register *******************/
5998 #define EXTI_EMR_MR0_Pos (0U)
5999 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6000 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6001 #define EXTI_EMR_MR1_Pos (1U)
6002 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6003 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6004 #define EXTI_EMR_MR2_Pos (2U)
6005 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6006 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6007 #define EXTI_EMR_MR3_Pos (3U)
6008 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6009 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6010 #define EXTI_EMR_MR4_Pos (4U)
6011 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6012 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6013 #define EXTI_EMR_MR5_Pos (5U)
6014 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6015 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6016 #define EXTI_EMR_MR6_Pos (6U)
6017 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6018 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6019 #define EXTI_EMR_MR7_Pos (7U)
6020 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6021 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6022 #define EXTI_EMR_MR8_Pos (8U)
6023 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6024 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6025 #define EXTI_EMR_MR9_Pos (9U)
6026 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6027 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6028 #define EXTI_EMR_MR10_Pos (10U)
6029 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6030 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6031 #define EXTI_EMR_MR11_Pos (11U)
6032 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6033 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6034 #define EXTI_EMR_MR12_Pos (12U)
6035 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6036 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6037 #define EXTI_EMR_MR13_Pos (13U)
6038 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6039 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6040 #define EXTI_EMR_MR14_Pos (14U)
6041 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6042 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6043 #define EXTI_EMR_MR15_Pos (15U)
6044 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6045 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6046 #define EXTI_EMR_MR16_Pos (16U)
6047 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6048 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6049 #define EXTI_EMR_MR17_Pos (17U)
6050 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6051 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6052 #define EXTI_EMR_MR18_Pos (18U)
6053 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6054 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6055 #define EXTI_EMR_MR19_Pos (19U)
6056 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6057 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6058 #define EXTI_EMR_MR20_Pos (20U)
6059 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6060 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6061 #define EXTI_EMR_MR21_Pos (21U)
6062 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6063 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6064 #define EXTI_EMR_MR22_Pos (22U)
6065 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6066 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6068 /* Reference Defines */
6069 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6070 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6071 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6072 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6073 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6074 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6075 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6076 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6077 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6078 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6079 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6080 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6081 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6082 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6083 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6084 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6085 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6086 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6087 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6088 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6089 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6090 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6091 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6092 
6093 /****************** Bit definition for EXTI_RTSR register *******************/
6094 #define EXTI_RTSR_TR0_Pos (0U)
6095 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6096 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6097 #define EXTI_RTSR_TR1_Pos (1U)
6098 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6099 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6100 #define EXTI_RTSR_TR2_Pos (2U)
6101 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6102 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6103 #define EXTI_RTSR_TR3_Pos (3U)
6104 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6105 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6106 #define EXTI_RTSR_TR4_Pos (4U)
6107 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6108 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6109 #define EXTI_RTSR_TR5_Pos (5U)
6110 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6111 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6112 #define EXTI_RTSR_TR6_Pos (6U)
6113 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6114 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6115 #define EXTI_RTSR_TR7_Pos (7U)
6116 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6117 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6118 #define EXTI_RTSR_TR8_Pos (8U)
6119 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6120 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6121 #define EXTI_RTSR_TR9_Pos (9U)
6122 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6123 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6124 #define EXTI_RTSR_TR10_Pos (10U)
6125 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6126 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6127 #define EXTI_RTSR_TR11_Pos (11U)
6128 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6129 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6130 #define EXTI_RTSR_TR12_Pos (12U)
6131 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6132 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6133 #define EXTI_RTSR_TR13_Pos (13U)
6134 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6135 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6136 #define EXTI_RTSR_TR14_Pos (14U)
6137 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6138 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6139 #define EXTI_RTSR_TR15_Pos (15U)
6140 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6141 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6142 #define EXTI_RTSR_TR16_Pos (16U)
6143 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6144 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6145 #define EXTI_RTSR_TR17_Pos (17U)
6146 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6147 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6148 #define EXTI_RTSR_TR18_Pos (18U)
6149 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6150 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6151 #define EXTI_RTSR_TR19_Pos (19U)
6152 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6153 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6154 #define EXTI_RTSR_TR20_Pos (20U)
6155 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6156 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6157 #define EXTI_RTSR_TR21_Pos (21U)
6158 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6159 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6160 #define EXTI_RTSR_TR22_Pos (22U)
6161 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6162 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6164 /****************** Bit definition for EXTI_FTSR register *******************/
6165 #define EXTI_FTSR_TR0_Pos (0U)
6166 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6167 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6168 #define EXTI_FTSR_TR1_Pos (1U)
6169 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6170 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6171 #define EXTI_FTSR_TR2_Pos (2U)
6172 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6173 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6174 #define EXTI_FTSR_TR3_Pos (3U)
6175 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6176 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6177 #define EXTI_FTSR_TR4_Pos (4U)
6178 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6179 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6180 #define EXTI_FTSR_TR5_Pos (5U)
6181 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6182 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6183 #define EXTI_FTSR_TR6_Pos (6U)
6184 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6185 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6186 #define EXTI_FTSR_TR7_Pos (7U)
6187 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6188 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6189 #define EXTI_FTSR_TR8_Pos (8U)
6190 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6191 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6192 #define EXTI_FTSR_TR9_Pos (9U)
6193 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6194 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6195 #define EXTI_FTSR_TR10_Pos (10U)
6196 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6197 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6198 #define EXTI_FTSR_TR11_Pos (11U)
6199 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6200 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6201 #define EXTI_FTSR_TR12_Pos (12U)
6202 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6203 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6204 #define EXTI_FTSR_TR13_Pos (13U)
6205 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6206 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6207 #define EXTI_FTSR_TR14_Pos (14U)
6208 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6209 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6210 #define EXTI_FTSR_TR15_Pos (15U)
6211 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6212 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6213 #define EXTI_FTSR_TR16_Pos (16U)
6214 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6215 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6216 #define EXTI_FTSR_TR17_Pos (17U)
6217 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6218 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6219 #define EXTI_FTSR_TR18_Pos (18U)
6220 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6221 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6222 #define EXTI_FTSR_TR19_Pos (19U)
6223 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6224 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6225 #define EXTI_FTSR_TR20_Pos (20U)
6226 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6227 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6228 #define EXTI_FTSR_TR21_Pos (21U)
6229 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6230 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6231 #define EXTI_FTSR_TR22_Pos (22U)
6232 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6233 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6235 /****************** Bit definition for EXTI_SWIER register ******************/
6236 #define EXTI_SWIER_SWIER0_Pos (0U)
6237 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6238 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6239 #define EXTI_SWIER_SWIER1_Pos (1U)
6240 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6241 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6242 #define EXTI_SWIER_SWIER2_Pos (2U)
6243 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6244 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6245 #define EXTI_SWIER_SWIER3_Pos (3U)
6246 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6247 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6248 #define EXTI_SWIER_SWIER4_Pos (4U)
6249 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6250 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6251 #define EXTI_SWIER_SWIER5_Pos (5U)
6252 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6253 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6254 #define EXTI_SWIER_SWIER6_Pos (6U)
6255 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6256 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6257 #define EXTI_SWIER_SWIER7_Pos (7U)
6258 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6259 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6260 #define EXTI_SWIER_SWIER8_Pos (8U)
6261 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6262 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6263 #define EXTI_SWIER_SWIER9_Pos (9U)
6264 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6265 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6266 #define EXTI_SWIER_SWIER10_Pos (10U)
6267 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6268 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6269 #define EXTI_SWIER_SWIER11_Pos (11U)
6270 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6271 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6272 #define EXTI_SWIER_SWIER12_Pos (12U)
6273 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6274 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6275 #define EXTI_SWIER_SWIER13_Pos (13U)
6276 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6277 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6278 #define EXTI_SWIER_SWIER14_Pos (14U)
6279 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6280 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6281 #define EXTI_SWIER_SWIER15_Pos (15U)
6282 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6283 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6284 #define EXTI_SWIER_SWIER16_Pos (16U)
6285 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6286 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6287 #define EXTI_SWIER_SWIER17_Pos (17U)
6288 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6289 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6290 #define EXTI_SWIER_SWIER18_Pos (18U)
6291 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6292 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6293 #define EXTI_SWIER_SWIER19_Pos (19U)
6294 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6295 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6296 #define EXTI_SWIER_SWIER20_Pos (20U)
6297 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6298 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6299 #define EXTI_SWIER_SWIER21_Pos (21U)
6300 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6301 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6302 #define EXTI_SWIER_SWIER22_Pos (22U)
6303 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6304 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6306 /******************* Bit definition for EXTI_PR register ********************/
6307 #define EXTI_PR_PR0_Pos (0U)
6308 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6309 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6310 #define EXTI_PR_PR1_Pos (1U)
6311 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6312 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6313 #define EXTI_PR_PR2_Pos (2U)
6314 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6315 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6316 #define EXTI_PR_PR3_Pos (3U)
6317 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6318 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6319 #define EXTI_PR_PR4_Pos (4U)
6320 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6321 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6322 #define EXTI_PR_PR5_Pos (5U)
6323 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6324 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6325 #define EXTI_PR_PR6_Pos (6U)
6326 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6327 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6328 #define EXTI_PR_PR7_Pos (7U)
6329 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6330 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6331 #define EXTI_PR_PR8_Pos (8U)
6332 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6333 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6334 #define EXTI_PR_PR9_Pos (9U)
6335 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6336 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6337 #define EXTI_PR_PR10_Pos (10U)
6338 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6339 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6340 #define EXTI_PR_PR11_Pos (11U)
6341 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6342 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6343 #define EXTI_PR_PR12_Pos (12U)
6344 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6345 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6346 #define EXTI_PR_PR13_Pos (13U)
6347 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6348 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6349 #define EXTI_PR_PR14_Pos (14U)
6350 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6351 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6352 #define EXTI_PR_PR15_Pos (15U)
6353 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6354 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6355 #define EXTI_PR_PR16_Pos (16U)
6356 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6357 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6358 #define EXTI_PR_PR17_Pos (17U)
6359 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6360 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6361 #define EXTI_PR_PR18_Pos (18U)
6362 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6363 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6364 #define EXTI_PR_PR19_Pos (19U)
6365 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6366 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6367 #define EXTI_PR_PR20_Pos (20U)
6368 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6369 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6370 #define EXTI_PR_PR21_Pos (21U)
6371 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6372 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6373 #define EXTI_PR_PR22_Pos (22U)
6374 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6375 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6377 /******************************************************************************/
6378 /* */
6379 /* FLASH */
6380 /* */
6381 /******************************************************************************/
6382 /******************* Bits definition for FLASH_ACR register *****************/
6383 #define FLASH_ACR_LATENCY_Pos (0U)
6384 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6385 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6386 #define FLASH_ACR_LATENCY_0WS 0x00000000U
6387 #define FLASH_ACR_LATENCY_1WS 0x00000001U
6388 #define FLASH_ACR_LATENCY_2WS 0x00000002U
6389 #define FLASH_ACR_LATENCY_3WS 0x00000003U
6390 #define FLASH_ACR_LATENCY_4WS 0x00000004U
6391 #define FLASH_ACR_LATENCY_5WS 0x00000005U
6392 #define FLASH_ACR_LATENCY_6WS 0x00000006U
6393 #define FLASH_ACR_LATENCY_7WS 0x00000007U
6394 
6395 
6396 #define FLASH_ACR_PRFTEN_Pos (8U)
6397 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6398 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6399 #define FLASH_ACR_ICEN_Pos (9U)
6400 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6401 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6402 #define FLASH_ACR_DCEN_Pos (10U)
6403 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6404 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6405 #define FLASH_ACR_ICRST_Pos (11U)
6406 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6407 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6408 #define FLASH_ACR_DCRST_Pos (12U)
6409 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6410 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6411 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6412 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6413 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6414 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6415 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6416 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6417 
6418 /******************* Bits definition for FLASH_SR register ******************/
6419 #define FLASH_SR_EOP_Pos (0U)
6420 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6421 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6422 #define FLASH_SR_SOP_Pos (1U)
6423 #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
6424 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
6425 #define FLASH_SR_WRPERR_Pos (4U)
6426 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6427 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6428 #define FLASH_SR_PGAERR_Pos (5U)
6429 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6430 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6431 #define FLASH_SR_PGPERR_Pos (6U)
6432 #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6433 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6434 #define FLASH_SR_PGSERR_Pos (7U)
6435 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6436 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6437 #define FLASH_SR_BSY_Pos (16U)
6438 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6439 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6440 
6441 /******************* Bits definition for FLASH_CR register ******************/
6442 #define FLASH_CR_PG_Pos (0U)
6443 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6444 #define FLASH_CR_PG FLASH_CR_PG_Msk
6445 #define FLASH_CR_SER_Pos (1U)
6446 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6447 #define FLASH_CR_SER FLASH_CR_SER_Msk
6448 #define FLASH_CR_MER_Pos (2U)
6449 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6450 #define FLASH_CR_MER FLASH_CR_MER_Msk
6451 #define FLASH_CR_SNB_Pos (3U)
6452 #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
6453 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
6454 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6455 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6456 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6457 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6458 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
6459 #define FLASH_CR_PSIZE_Pos (8U)
6460 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6461 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6462 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6463 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6464 #define FLASH_CR_STRT_Pos (16U)
6465 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6466 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6467 #define FLASH_CR_EOPIE_Pos (24U)
6468 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6469 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6470 #define FLASH_CR_ERRIE_Pos (25U)
6471 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6472 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6473 #define FLASH_CR_LOCK_Pos (31U)
6474 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6475 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6476 
6477 /******************* Bits definition for FLASH_OPTCR register ***************/
6478 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
6479 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6480 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6481 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
6482 #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6483 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6484 
6485 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6486 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6487 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
6488 #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6489 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6490 #define FLASH_OPTCR_WDG_SW_Pos (5U)
6491 #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6492 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6493 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
6494 #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6495 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6496 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6497 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6498 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6499 #define FLASH_OPTCR_RDP_Pos (8U)
6500 #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6501 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6502 #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6503 #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6504 #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6505 #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6506 #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6507 #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6508 #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6509 #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6510 #define FLASH_OPTCR_nWRP_Pos (16U)
6511 #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
6512 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6513 #define FLASH_OPTCR_nWRP_0 0x00010000U
6514 #define FLASH_OPTCR_nWRP_1 0x00020000U
6515 #define FLASH_OPTCR_nWRP_2 0x00040000U
6516 #define FLASH_OPTCR_nWRP_3 0x00080000U
6517 #define FLASH_OPTCR_nWRP_4 0x00100000U
6518 #define FLASH_OPTCR_nWRP_5 0x00200000U
6519 #define FLASH_OPTCR_nWRP_6 0x00400000U
6520 #define FLASH_OPTCR_nWRP_7 0x00800000U
6521 #define FLASH_OPTCR_nWRP_8 0x01000000U
6522 #define FLASH_OPTCR_nWRP_9 0x02000000U
6523 #define FLASH_OPTCR_nWRP_10 0x04000000U
6524 #define FLASH_OPTCR_nWRP_11 0x08000000U
6525 
6526 /****************** Bits definition for FLASH_OPTCR1 register ***************/
6527 #define FLASH_OPTCR1_nWRP_Pos (16U)
6528 #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
6529 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6530 #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
6531 #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
6532 #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
6533 #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
6534 #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
6535 #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
6536 #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
6537 #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
6538 #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
6539 #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
6540 #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
6541 #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
6543 /******************************************************************************/
6544 /* */
6545 /* Flexible Static Memory Controller */
6546 /* */
6547 /******************************************************************************/
6548 /****************** Bit definition for FSMC_BCR1 register *******************/
6549 #define FSMC_BCR1_MBKEN_Pos (0U)
6550 #define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
6551 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
6552 #define FSMC_BCR1_MUXEN_Pos (1U)
6553 #define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
6554 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
6556 #define FSMC_BCR1_MTYP_Pos (2U)
6557 #define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
6558 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
6559 #define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
6560 #define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
6562 #define FSMC_BCR1_MWID_Pos (4U)
6563 #define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
6564 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
6565 #define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
6566 #define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
6568 #define FSMC_BCR1_FACCEN_Pos (6U)
6569 #define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
6570 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
6571 #define FSMC_BCR1_BURSTEN_Pos (8U)
6572 #define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
6573 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
6574 #define FSMC_BCR1_WAITPOL_Pos (9U)
6575 #define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
6576 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
6577 #define FSMC_BCR1_WRAPMOD_Pos (10U)
6578 #define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
6579 #define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk
6580 #define FSMC_BCR1_WAITCFG_Pos (11U)
6581 #define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
6582 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
6583 #define FSMC_BCR1_WREN_Pos (12U)
6584 #define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
6585 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
6586 #define FSMC_BCR1_WAITEN_Pos (13U)
6587 #define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
6588 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
6589 #define FSMC_BCR1_EXTMOD_Pos (14U)
6590 #define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
6591 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
6592 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6593 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
6594 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
6595 #define FSMC_BCR1_CPSIZE_Pos (16U)
6596 #define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
6597 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
6598 #define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
6599 #define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
6600 #define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
6601 #define FSMC_BCR1_CBURSTRW_Pos (19U)
6602 #define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
6603 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
6605 /****************** Bit definition for FSMC_BCR2 register *******************/
6606 #define FSMC_BCR2_MBKEN_Pos (0U)
6607 #define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
6608 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
6609 #define FSMC_BCR2_MUXEN_Pos (1U)
6610 #define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
6611 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
6613 #define FSMC_BCR2_MTYP_Pos (2U)
6614 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
6615 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
6616 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
6617 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
6619 #define FSMC_BCR2_MWID_Pos (4U)
6620 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
6621 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
6622 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
6623 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
6625 #define FSMC_BCR2_FACCEN_Pos (6U)
6626 #define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
6627 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
6628 #define FSMC_BCR2_BURSTEN_Pos (8U)
6629 #define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
6630 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
6631 #define FSMC_BCR2_WAITPOL_Pos (9U)
6632 #define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
6633 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
6634 #define FSMC_BCR2_WRAPMOD_Pos (10U)
6635 #define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
6636 #define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk
6637 #define FSMC_BCR2_WAITCFG_Pos (11U)
6638 #define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
6639 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
6640 #define FSMC_BCR2_WREN_Pos (12U)
6641 #define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
6642 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
6643 #define FSMC_BCR2_WAITEN_Pos (13U)
6644 #define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
6645 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
6646 #define FSMC_BCR2_EXTMOD_Pos (14U)
6647 #define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
6648 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
6649 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6650 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
6651 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
6652 #define FSMC_BCR2_CPSIZE_Pos (16U)
6653 #define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
6654 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
6655 #define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
6656 #define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
6657 #define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
6658 #define FSMC_BCR2_CBURSTRW_Pos (19U)
6659 #define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
6660 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
6662 /****************** Bit definition for FSMC_BCR3 register *******************/
6663 #define FSMC_BCR3_MBKEN_Pos (0U)
6664 #define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
6665 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
6666 #define FSMC_BCR3_MUXEN_Pos (1U)
6667 #define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
6668 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
6670 #define FSMC_BCR3_MTYP_Pos (2U)
6671 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
6672 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
6673 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
6674 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
6676 #define FSMC_BCR3_MWID_Pos (4U)
6677 #define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
6678 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
6679 #define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
6680 #define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
6682 #define FSMC_BCR3_FACCEN_Pos (6U)
6683 #define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
6684 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
6685 #define FSMC_BCR3_BURSTEN_Pos (8U)
6686 #define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
6687 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
6688 #define FSMC_BCR3_WAITPOL_Pos (9U)
6689 #define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
6690 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
6691 #define FSMC_BCR3_WRAPMOD_Pos (10U)
6692 #define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
6693 #define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk
6694 #define FSMC_BCR3_WAITCFG_Pos (11U)
6695 #define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
6696 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
6697 #define FSMC_BCR3_WREN_Pos (12U)
6698 #define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
6699 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
6700 #define FSMC_BCR3_WAITEN_Pos (13U)
6701 #define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
6702 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
6703 #define FSMC_BCR3_EXTMOD_Pos (14U)
6704 #define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
6705 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
6706 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
6707 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
6708 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
6709 #define FSMC_BCR3_CPSIZE_Pos (16U)
6710 #define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
6711 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
6712 #define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
6713 #define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
6714 #define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
6715 #define FSMC_BCR3_CBURSTRW_Pos (19U)
6716 #define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
6717 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
6719 /****************** Bit definition for FSMC_BCR4 register *******************/
6720 #define FSMC_BCR4_MBKEN_Pos (0U)
6721 #define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
6722 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
6723 #define FSMC_BCR4_MUXEN_Pos (1U)
6724 #define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
6725 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
6727 #define FSMC_BCR4_MTYP_Pos (2U)
6728 #define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
6729 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
6730 #define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
6731 #define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
6733 #define FSMC_BCR4_MWID_Pos (4U)
6734 #define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
6735 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
6736 #define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
6737 #define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
6739 #define FSMC_BCR4_FACCEN_Pos (6U)
6740 #define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
6741 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
6742 #define FSMC_BCR4_BURSTEN_Pos (8U)
6743 #define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
6744 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
6745 #define FSMC_BCR4_WAITPOL_Pos (9U)
6746 #define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
6747 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
6748 #define FSMC_BCR4_WRAPMOD_Pos (10U)
6749 #define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
6750 #define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk
6751 #define FSMC_BCR4_WAITCFG_Pos (11U)
6752 #define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
6753 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
6754 #define FSMC_BCR4_WREN_Pos (12U)
6755 #define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
6756 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
6757 #define FSMC_BCR4_WAITEN_Pos (13U)
6758 #define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
6759 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
6760 #define FSMC_BCR4_EXTMOD_Pos (14U)
6761 #define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
6762 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
6763 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
6764 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
6765 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
6766 #define FSMC_BCR4_CPSIZE_Pos (16U)
6767 #define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
6768 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
6769 #define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
6770 #define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
6771 #define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
6772 #define FSMC_BCR4_CBURSTRW_Pos (19U)
6773 #define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
6774 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
6776 /****************** Bit definition for FSMC_BTR1 register ******************/
6777 #define FSMC_BTR1_ADDSET_Pos (0U)
6778 #define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
6779 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
6780 #define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
6781 #define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
6782 #define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
6783 #define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
6785 #define FSMC_BTR1_ADDHLD_Pos (4U)
6786 #define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
6787 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
6788 #define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
6789 #define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
6790 #define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
6791 #define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
6793 #define FSMC_BTR1_DATAST_Pos (8U)
6794 #define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
6795 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
6796 #define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
6797 #define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
6798 #define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
6799 #define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
6800 #define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
6801 #define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
6802 #define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
6803 #define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
6805 #define FSMC_BTR1_BUSTURN_Pos (16U)
6806 #define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
6807 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
6808 #define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
6809 #define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
6810 #define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
6811 #define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
6813 #define FSMC_BTR1_CLKDIV_Pos (20U)
6814 #define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
6815 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
6816 #define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
6817 #define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
6818 #define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
6819 #define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
6821 #define FSMC_BTR1_DATLAT_Pos (24U)
6822 #define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
6823 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
6824 #define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
6825 #define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
6826 #define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
6827 #define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
6829 #define FSMC_BTR1_ACCMOD_Pos (28U)
6830 #define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
6831 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
6832 #define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
6833 #define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
6835 /****************** Bit definition for FSMC_BTR2 register *******************/
6836 #define FSMC_BTR2_ADDSET_Pos (0U)
6837 #define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
6838 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
6839 #define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
6840 #define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
6841 #define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
6842 #define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
6844 #define FSMC_BTR2_ADDHLD_Pos (4U)
6845 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
6846 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
6847 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
6848 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
6849 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
6850 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
6852 #define FSMC_BTR2_DATAST_Pos (8U)
6853 #define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
6854 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
6855 #define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
6856 #define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
6857 #define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
6858 #define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
6859 #define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
6860 #define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
6861 #define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
6862 #define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
6864 #define FSMC_BTR2_BUSTURN_Pos (16U)
6865 #define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
6866 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
6867 #define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
6868 #define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
6869 #define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
6870 #define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
6872 #define FSMC_BTR2_CLKDIV_Pos (20U)
6873 #define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
6874 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
6875 #define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
6876 #define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
6877 #define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
6878 #define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
6880 #define FSMC_BTR2_DATLAT_Pos (24U)
6881 #define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
6882 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
6883 #define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
6884 #define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
6885 #define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
6886 #define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
6888 #define FSMC_BTR2_ACCMOD_Pos (28U)
6889 #define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
6890 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
6891 #define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
6892 #define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
6894 /******************* Bit definition for FSMC_BTR3 register *******************/
6895 #define FSMC_BTR3_ADDSET_Pos (0U)
6896 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
6897 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
6898 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
6899 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
6900 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
6901 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
6903 #define FSMC_BTR3_ADDHLD_Pos (4U)
6904 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
6905 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
6906 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
6907 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
6908 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
6909 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
6911 #define FSMC_BTR3_DATAST_Pos (8U)
6912 #define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
6913 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
6914 #define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
6915 #define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
6916 #define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
6917 #define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
6918 #define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
6919 #define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
6920 #define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
6921 #define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
6923 #define FSMC_BTR3_BUSTURN_Pos (16U)
6924 #define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
6925 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
6926 #define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
6927 #define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
6928 #define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
6929 #define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
6931 #define FSMC_BTR3_CLKDIV_Pos (20U)
6932 #define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
6933 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
6934 #define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
6935 #define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
6936 #define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
6937 #define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
6939 #define FSMC_BTR3_DATLAT_Pos (24U)
6940 #define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
6941 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
6942 #define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
6943 #define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
6944 #define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
6945 #define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
6947 #define FSMC_BTR3_ACCMOD_Pos (28U)
6948 #define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
6949 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
6950 #define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
6951 #define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
6953 /****************** Bit definition for FSMC_BTR4 register *******************/
6954 #define FSMC_BTR4_ADDSET_Pos (0U)
6955 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
6956 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
6957 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
6958 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
6959 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
6960 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
6962 #define FSMC_BTR4_ADDHLD_Pos (4U)
6963 #define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
6964 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
6965 #define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
6966 #define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
6967 #define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
6968 #define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
6970 #define FSMC_BTR4_DATAST_Pos (8U)
6971 #define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
6972 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
6973 #define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
6974 #define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
6975 #define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
6976 #define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
6977 #define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
6978 #define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
6979 #define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
6980 #define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
6982 #define FSMC_BTR4_BUSTURN_Pos (16U)
6983 #define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
6984 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
6985 #define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
6986 #define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
6987 #define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
6988 #define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
6990 #define FSMC_BTR4_CLKDIV_Pos (20U)
6991 #define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
6992 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
6993 #define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
6994 #define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
6995 #define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
6996 #define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
6998 #define FSMC_BTR4_DATLAT_Pos (24U)
6999 #define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7000 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7001 #define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7002 #define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7003 #define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7004 #define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7006 #define FSMC_BTR4_ACCMOD_Pos (28U)
7007 #define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7008 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7009 #define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7010 #define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7012 /****************** Bit definition for FSMC_BWTR1 register ******************/
7013 #define FSMC_BWTR1_ADDSET_Pos (0U)
7014 #define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7015 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7016 #define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7017 #define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7018 #define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7019 #define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7021 #define FSMC_BWTR1_ADDHLD_Pos (4U)
7022 #define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7023 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7024 #define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7025 #define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7026 #define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7027 #define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7029 #define FSMC_BWTR1_DATAST_Pos (8U)
7030 #define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7031 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7032 #define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7033 #define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7034 #define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7035 #define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7036 #define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7037 #define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7038 #define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7039 #define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7041 #define FSMC_BWTR1_BUSTURN_Pos (16U)
7042 #define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7043 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7044 #define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7045 #define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7046 #define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7047 #define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7049 #define FSMC_BWTR1_ACCMOD_Pos (28U)
7050 #define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7051 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7052 #define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7053 #define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7055 /****************** Bit definition for FSMC_BWTR2 register ******************/
7056 #define FSMC_BWTR2_ADDSET_Pos (0U)
7057 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7058 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7059 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7060 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7061 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7062 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7064 #define FSMC_BWTR2_ADDHLD_Pos (4U)
7065 #define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7066 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7067 #define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7068 #define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7069 #define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7070 #define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7072 #define FSMC_BWTR2_DATAST_Pos (8U)
7073 #define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7074 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7075 #define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7076 #define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7077 #define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7078 #define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7079 #define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7080 #define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7081 #define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7082 #define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7084 #define FSMC_BWTR2_BUSTURN_Pos (16U)
7085 #define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7086 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7087 #define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7088 #define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7089 #define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7090 #define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7092 #define FSMC_BWTR2_ACCMOD_Pos (28U)
7093 #define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7094 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7095 #define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7096 #define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7098 /****************** Bit definition for FSMC_BWTR3 register ******************/
7099 #define FSMC_BWTR3_ADDSET_Pos (0U)
7100 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7101 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7102 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7103 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7104 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7105 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7107 #define FSMC_BWTR3_ADDHLD_Pos (4U)
7108 #define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7109 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7110 #define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7111 #define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7112 #define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7113 #define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7115 #define FSMC_BWTR3_DATAST_Pos (8U)
7116 #define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7117 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7118 #define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7119 #define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7120 #define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7121 #define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7122 #define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7123 #define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7124 #define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7125 #define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7127 #define FSMC_BWTR3_BUSTURN_Pos (16U)
7128 #define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7129 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7130 #define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7131 #define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7132 #define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7133 #define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7135 #define FSMC_BWTR3_ACCMOD_Pos (28U)
7136 #define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7137 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7138 #define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7139 #define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7141 /****************** Bit definition for FSMC_BWTR4 register ******************/
7142 #define FSMC_BWTR4_ADDSET_Pos (0U)
7143 #define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7144 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7145 #define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7146 #define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7147 #define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7148 #define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7150 #define FSMC_BWTR4_ADDHLD_Pos (4U)
7151 #define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7152 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7153 #define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7154 #define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7155 #define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7156 #define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7158 #define FSMC_BWTR4_DATAST_Pos (8U)
7159 #define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7160 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7161 #define FSMC_BWTR4_DATAST_0 0x00000100U
7162 #define FSMC_BWTR4_DATAST_1 0x00000200U
7163 #define FSMC_BWTR4_DATAST_2 0x00000400U
7164 #define FSMC_BWTR4_DATAST_3 0x00000800U
7165 #define FSMC_BWTR4_DATAST_4 0x00001000U
7166 #define FSMC_BWTR4_DATAST_5 0x00002000U
7167 #define FSMC_BWTR4_DATAST_6 0x00004000U
7168 #define FSMC_BWTR4_DATAST_7 0x00008000U
7170 #define FSMC_BWTR4_BUSTURN_Pos (16U)
7171 #define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7172 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7173 #define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7174 #define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7175 #define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7176 #define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7178 #define FSMC_BWTR4_ACCMOD_Pos (28U)
7179 #define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7180 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7181 #define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7182 #define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7184 /****************** Bit definition for FSMC_PCR2 register *******************/
7185 #define FSMC_PCR2_PWAITEN_Pos (1U)
7186 #define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)
7187 #define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk
7188 #define FSMC_PCR2_PBKEN_Pos (2U)
7189 #define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)
7190 #define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk
7191 #define FSMC_PCR2_PTYP_Pos (3U)
7192 #define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)
7193 #define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk
7195 #define FSMC_PCR2_PWID_Pos (4U)
7196 #define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)
7197 #define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk
7198 #define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)
7199 #define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)
7201 #define FSMC_PCR2_ECCEN_Pos (6U)
7202 #define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)
7203 #define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk
7205 #define FSMC_PCR2_TCLR_Pos (9U)
7206 #define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)
7207 #define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk
7208 #define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)
7209 #define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)
7210 #define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)
7211 #define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)
7213 #define FSMC_PCR2_TAR_Pos (13U)
7214 #define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)
7215 #define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk
7216 #define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)
7217 #define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)
7218 #define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)
7219 #define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)
7221 #define FSMC_PCR2_ECCPS_Pos (17U)
7222 #define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)
7223 #define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk
7224 #define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)
7225 #define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)
7226 #define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)
7228 /****************** Bit definition for FSMC_PCR3 register *******************/
7229 #define FSMC_PCR3_PWAITEN_Pos (1U)
7230 #define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)
7231 #define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk
7232 #define FSMC_PCR3_PBKEN_Pos (2U)
7233 #define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)
7234 #define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk
7235 #define FSMC_PCR3_PTYP_Pos (3U)
7236 #define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)
7237 #define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk
7239 #define FSMC_PCR3_PWID_Pos (4U)
7240 #define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)
7241 #define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk
7242 #define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)
7243 #define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)
7245 #define FSMC_PCR3_ECCEN_Pos (6U)
7246 #define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)
7247 #define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk
7249 #define FSMC_PCR3_TCLR_Pos (9U)
7250 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)
7251 #define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk
7252 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)
7253 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)
7254 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)
7255 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)
7257 #define FSMC_PCR3_TAR_Pos (13U)
7258 #define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)
7259 #define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk
7260 #define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)
7261 #define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)
7262 #define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)
7263 #define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)
7265 #define FSMC_PCR3_ECCPS_Pos (17U)
7266 #define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)
7267 #define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk
7268 #define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)
7269 #define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)
7270 #define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)
7272 /****************** Bit definition for FSMC_PCR4 register *******************/
7273 #define FSMC_PCR4_PWAITEN_Pos (1U)
7274 #define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)
7275 #define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk
7276 #define FSMC_PCR4_PBKEN_Pos (2U)
7277 #define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)
7278 #define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk
7279 #define FSMC_PCR4_PTYP_Pos (3U)
7280 #define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)
7281 #define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk
7283 #define FSMC_PCR4_PWID_Pos (4U)
7284 #define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)
7285 #define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk
7286 #define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)
7287 #define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)
7289 #define FSMC_PCR4_ECCEN_Pos (6U)
7290 #define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)
7291 #define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk
7293 #define FSMC_PCR4_TCLR_Pos (9U)
7294 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)
7295 #define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk
7296 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)
7297 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)
7298 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)
7299 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)
7301 #define FSMC_PCR4_TAR_Pos (13U)
7302 #define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)
7303 #define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk
7304 #define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)
7305 #define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)
7306 #define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)
7307 #define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)
7309 #define FSMC_PCR4_ECCPS_Pos (17U)
7310 #define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)
7311 #define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk
7312 #define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)
7313 #define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)
7314 #define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)
7316 /******************* Bit definition for FSMC_SR2 register *******************/
7317 #define FSMC_SR2_IRS_Pos (0U)
7318 #define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)
7319 #define FSMC_SR2_IRS FSMC_SR2_IRS_Msk
7320 #define FSMC_SR2_ILS_Pos (1U)
7321 #define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)
7322 #define FSMC_SR2_ILS FSMC_SR2_ILS_Msk
7323 #define FSMC_SR2_IFS_Pos (2U)
7324 #define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)
7325 #define FSMC_SR2_IFS FSMC_SR2_IFS_Msk
7326 #define FSMC_SR2_IREN_Pos (3U)
7327 #define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)
7328 #define FSMC_SR2_IREN FSMC_SR2_IREN_Msk
7329 #define FSMC_SR2_ILEN_Pos (4U)
7330 #define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)
7331 #define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk
7332 #define FSMC_SR2_IFEN_Pos (5U)
7333 #define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)
7334 #define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk
7335 #define FSMC_SR2_FEMPT_Pos (6U)
7336 #define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)
7337 #define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk
7339 /******************* Bit definition for FSMC_SR3 register *******************/
7340 #define FSMC_SR3_IRS_Pos (0U)
7341 #define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)
7342 #define FSMC_SR3_IRS FSMC_SR3_IRS_Msk
7343 #define FSMC_SR3_ILS_Pos (1U)
7344 #define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)
7345 #define FSMC_SR3_ILS FSMC_SR3_ILS_Msk
7346 #define FSMC_SR3_IFS_Pos (2U)
7347 #define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)
7348 #define FSMC_SR3_IFS FSMC_SR3_IFS_Msk
7349 #define FSMC_SR3_IREN_Pos (3U)
7350 #define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)
7351 #define FSMC_SR3_IREN FSMC_SR3_IREN_Msk
7352 #define FSMC_SR3_ILEN_Pos (4U)
7353 #define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)
7354 #define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk
7355 #define FSMC_SR3_IFEN_Pos (5U)
7356 #define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)
7357 #define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk
7358 #define FSMC_SR3_FEMPT_Pos (6U)
7359 #define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)
7360 #define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk
7362 /******************* Bit definition for FSMC_SR4 register *******************/
7363 #define FSMC_SR4_IRS_Pos (0U)
7364 #define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)
7365 #define FSMC_SR4_IRS FSMC_SR4_IRS_Msk
7366 #define FSMC_SR4_ILS_Pos (1U)
7367 #define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)
7368 #define FSMC_SR4_ILS FSMC_SR4_ILS_Msk
7369 #define FSMC_SR4_IFS_Pos (2U)
7370 #define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)
7371 #define FSMC_SR4_IFS FSMC_SR4_IFS_Msk
7372 #define FSMC_SR4_IREN_Pos (3U)
7373 #define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)
7374 #define FSMC_SR4_IREN FSMC_SR4_IREN_Msk
7375 #define FSMC_SR4_ILEN_Pos (4U)
7376 #define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)
7377 #define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk
7378 #define FSMC_SR4_IFEN_Pos (5U)
7379 #define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)
7380 #define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk
7381 #define FSMC_SR4_FEMPT_Pos (6U)
7382 #define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)
7383 #define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk
7385 /****************** Bit definition for FSMC_PMEM2 register ******************/
7386 #define FSMC_PMEM2_MEMSET2_Pos (0U)
7387 #define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
7388 #define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk
7389 #define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
7390 #define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
7391 #define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
7392 #define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
7393 #define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
7394 #define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
7395 #define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
7396 #define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
7398 #define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7399 #define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
7400 #define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk
7401 #define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
7402 #define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
7403 #define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
7404 #define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
7405 #define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
7406 #define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
7407 #define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
7408 #define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
7410 #define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7411 #define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
7412 #define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk
7413 #define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
7414 #define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
7415 #define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
7416 #define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
7417 #define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
7418 #define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
7419 #define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
7420 #define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
7422 #define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7423 #define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
7424 #define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk
7425 #define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
7426 #define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
7427 #define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
7428 #define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
7429 #define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
7430 #define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
7431 #define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
7432 #define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
7434 /****************** Bit definition for FSMC_PMEM3 register ******************/
7435 #define FSMC_PMEM3_MEMSET3_Pos (0U)
7436 #define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
7437 #define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk
7438 #define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
7439 #define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
7440 #define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
7441 #define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
7442 #define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
7443 #define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
7444 #define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
7445 #define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
7447 #define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7448 #define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
7449 #define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk
7450 #define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
7451 #define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
7452 #define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
7453 #define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
7454 #define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
7455 #define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
7456 #define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
7457 #define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
7459 #define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7460 #define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
7461 #define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk
7462 #define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
7463 #define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
7464 #define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
7465 #define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
7466 #define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
7467 #define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
7468 #define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
7469 #define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
7471 #define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7472 #define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
7473 #define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk
7474 #define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
7475 #define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
7476 #define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
7477 #define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
7478 #define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
7479 #define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
7480 #define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
7481 #define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
7483 /****************** Bit definition for FSMC_PMEM4 register ******************/
7484 #define FSMC_PMEM4_MEMSET4_Pos (0U)
7485 #define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
7486 #define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk
7487 #define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
7488 #define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
7489 #define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
7490 #define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
7491 #define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
7492 #define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
7493 #define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
7494 #define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
7496 #define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7497 #define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
7498 #define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk
7499 #define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
7500 #define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
7501 #define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
7502 #define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
7503 #define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
7504 #define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
7505 #define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
7506 #define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
7508 #define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7509 #define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
7510 #define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk
7511 #define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
7512 #define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
7513 #define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
7514 #define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
7515 #define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
7516 #define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
7517 #define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
7518 #define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
7520 #define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7521 #define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
7522 #define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk
7523 #define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
7524 #define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
7525 #define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
7526 #define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
7527 #define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
7528 #define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
7529 #define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
7530 #define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
7532 /****************** Bit definition for FSMC_PATT2 register ******************/
7533 #define FSMC_PATT2_ATTSET2_Pos (0U)
7534 #define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
7535 #define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk
7536 #define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)
7537 #define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)
7538 #define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)
7539 #define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)
7540 #define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)
7541 #define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)
7542 #define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)
7543 #define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)
7545 #define FSMC_PATT2_ATTWAIT2_Pos (8U)
7546 #define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
7547 #define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk
7548 #define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
7549 #define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
7550 #define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
7551 #define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
7552 #define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
7553 #define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
7554 #define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
7555 #define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
7557 #define FSMC_PATT2_ATTHOLD2_Pos (16U)
7558 #define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
7559 #define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk
7560 #define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
7561 #define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
7562 #define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
7563 #define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
7564 #define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
7565 #define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
7566 #define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
7567 #define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
7569 #define FSMC_PATT2_ATTHIZ2_Pos (24U)
7570 #define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
7571 #define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk
7572 #define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
7573 #define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
7574 #define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
7575 #define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
7576 #define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
7577 #define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
7578 #define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
7579 #define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
7581 /****************** Bit definition for FSMC_PATT3 register ******************/
7582 #define FSMC_PATT3_ATTSET3_Pos (0U)
7583 #define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
7584 #define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk
7585 #define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)
7586 #define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)
7587 #define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)
7588 #define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)
7589 #define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)
7590 #define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)
7591 #define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)
7592 #define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)
7594 #define FSMC_PATT3_ATTWAIT3_Pos (8U)
7595 #define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
7596 #define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk
7597 #define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
7598 #define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
7599 #define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
7600 #define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
7601 #define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
7602 #define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
7603 #define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
7604 #define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
7606 #define FSMC_PATT3_ATTHOLD3_Pos (16U)
7607 #define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
7608 #define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk
7609 #define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
7610 #define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
7611 #define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
7612 #define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
7613 #define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
7614 #define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
7615 #define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
7616 #define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
7618 #define FSMC_PATT3_ATTHIZ3_Pos (24U)
7619 #define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
7620 #define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk
7621 #define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
7622 #define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
7623 #define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
7624 #define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
7625 #define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
7626 #define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
7627 #define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
7628 #define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
7630 /****************** Bit definition for FSMC_PATT4 register ******************/
7631 #define FSMC_PATT4_ATTSET4_Pos (0U)
7632 #define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
7633 #define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk
7634 #define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)
7635 #define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)
7636 #define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)
7637 #define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)
7638 #define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)
7639 #define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)
7640 #define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)
7641 #define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)
7643 #define FSMC_PATT4_ATTWAIT4_Pos (8U)
7644 #define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
7645 #define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk
7646 #define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
7647 #define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
7648 #define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
7649 #define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
7650 #define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
7651 #define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
7652 #define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
7653 #define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
7655 #define FSMC_PATT4_ATTHOLD4_Pos (16U)
7656 #define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
7657 #define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk
7658 #define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
7659 #define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
7660 #define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
7661 #define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
7662 #define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
7663 #define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
7664 #define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
7665 #define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
7667 #define FSMC_PATT4_ATTHIZ4_Pos (24U)
7668 #define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
7669 #define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk
7670 #define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
7671 #define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
7672 #define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
7673 #define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
7674 #define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
7675 #define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
7676 #define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
7677 #define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
7679 /****************** Bit definition for FSMC_PIO4 register *******************/
7680 #define FSMC_PIO4_IOSET4_Pos (0U)
7681 #define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)
7682 #define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk
7683 #define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)
7684 #define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)
7685 #define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)
7686 #define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)
7687 #define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)
7688 #define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)
7689 #define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)
7690 #define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)
7692 #define FSMC_PIO4_IOWAIT4_Pos (8U)
7693 #define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
7694 #define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk
7695 #define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
7696 #define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
7697 #define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
7698 #define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
7699 #define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
7700 #define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
7701 #define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
7702 #define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
7704 #define FSMC_PIO4_IOHOLD4_Pos (16U)
7705 #define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
7706 #define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk
7707 #define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
7708 #define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
7709 #define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
7710 #define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
7711 #define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
7712 #define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
7713 #define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
7714 #define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
7716 #define FSMC_PIO4_IOHIZ4_Pos (24U)
7717 #define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
7718 #define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk
7719 #define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
7720 #define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
7721 #define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
7722 #define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
7723 #define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
7724 #define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
7725 #define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
7726 #define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
7728 /****************** Bit definition for FSMC_ECCR2 register ******************/
7729 #define FSMC_ECCR2_ECC2_Pos (0U)
7730 #define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
7731 #define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk
7733 /****************** Bit definition for FSMC_ECCR3 register ******************/
7734 #define FSMC_ECCR3_ECC3_Pos (0U)
7735 #define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
7736 #define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk
7738 /******************************************************************************/
7739 /* */
7740 /* General Purpose I/O */
7741 /* */
7742 /******************************************************************************/
7743 /****************** Bits definition for GPIO_MODER register *****************/
7744 #define GPIO_MODER_MODER0_Pos (0U)
7745 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
7746 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
7747 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
7748 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
7749 #define GPIO_MODER_MODER1_Pos (2U)
7750 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
7751 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
7752 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
7753 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
7754 #define GPIO_MODER_MODER2_Pos (4U)
7755 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
7756 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
7757 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
7758 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
7759 #define GPIO_MODER_MODER3_Pos (6U)
7760 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
7761 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
7762 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
7763 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
7764 #define GPIO_MODER_MODER4_Pos (8U)
7765 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
7766 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
7767 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
7768 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
7769 #define GPIO_MODER_MODER5_Pos (10U)
7770 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
7771 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
7772 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
7773 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
7774 #define GPIO_MODER_MODER6_Pos (12U)
7775 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
7776 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
7777 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
7778 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
7779 #define GPIO_MODER_MODER7_Pos (14U)
7780 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
7781 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
7782 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
7783 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
7784 #define GPIO_MODER_MODER8_Pos (16U)
7785 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
7786 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
7787 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
7788 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
7789 #define GPIO_MODER_MODER9_Pos (18U)
7790 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
7791 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
7792 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
7793 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
7794 #define GPIO_MODER_MODER10_Pos (20U)
7795 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
7796 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
7797 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
7798 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
7799 #define GPIO_MODER_MODER11_Pos (22U)
7800 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
7801 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
7802 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
7803 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
7804 #define GPIO_MODER_MODER12_Pos (24U)
7805 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
7806 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
7807 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
7808 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
7809 #define GPIO_MODER_MODER13_Pos (26U)
7810 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
7811 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
7812 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
7813 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
7814 #define GPIO_MODER_MODER14_Pos (28U)
7815 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
7816 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
7817 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
7818 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
7819 #define GPIO_MODER_MODER15_Pos (30U)
7820 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
7821 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
7822 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
7823 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
7825 /* Legacy defines */
7826 #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
7827 #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
7828 #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
7829 #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
7830 #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
7831 #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
7832 #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
7833 #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
7834 #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
7835 #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
7836 #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
7837 #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
7838 #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
7839 #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
7840 #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
7841 #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
7842 #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
7843 #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
7844 #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
7845 #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
7846 #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
7847 #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
7848 #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
7849 #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
7850 #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
7851 #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
7852 #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
7853 #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
7854 #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
7855 #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
7856 #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
7857 #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
7858 #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
7859 #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
7860 #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
7861 #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
7862 #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
7863 #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
7864 #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
7865 #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
7866 #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
7867 #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
7868 #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
7869 #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
7870 #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
7871 #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
7872 #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
7873 #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
7874 #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
7875 #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
7876 #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
7877 #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
7878 #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
7879 #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
7880 #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
7881 #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
7882 #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
7883 #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
7884 #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
7885 #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
7886 #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
7887 #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
7888 #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
7889 #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
7890 #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
7891 #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
7892 #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
7893 #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
7894 #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
7895 #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
7896 #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
7897 #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
7898 #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
7899 #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
7900 #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
7901 #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
7902 #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
7903 #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
7904 #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
7905 #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
7906 
7907 /****************** Bits definition for GPIO_OTYPER register ****************/
7908 #define GPIO_OTYPER_OT0_Pos (0U)
7909 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
7910 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7911 #define GPIO_OTYPER_OT1_Pos (1U)
7912 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
7913 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7914 #define GPIO_OTYPER_OT2_Pos (2U)
7915 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
7916 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7917 #define GPIO_OTYPER_OT3_Pos (3U)
7918 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
7919 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7920 #define GPIO_OTYPER_OT4_Pos (4U)
7921 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
7922 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7923 #define GPIO_OTYPER_OT5_Pos (5U)
7924 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
7925 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7926 #define GPIO_OTYPER_OT6_Pos (6U)
7927 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
7928 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7929 #define GPIO_OTYPER_OT7_Pos (7U)
7930 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
7931 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7932 #define GPIO_OTYPER_OT8_Pos (8U)
7933 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
7934 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7935 #define GPIO_OTYPER_OT9_Pos (9U)
7936 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
7937 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7938 #define GPIO_OTYPER_OT10_Pos (10U)
7939 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
7940 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7941 #define GPIO_OTYPER_OT11_Pos (11U)
7942 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
7943 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7944 #define GPIO_OTYPER_OT12_Pos (12U)
7945 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
7946 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7947 #define GPIO_OTYPER_OT13_Pos (13U)
7948 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
7949 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7950 #define GPIO_OTYPER_OT14_Pos (14U)
7951 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
7952 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7953 #define GPIO_OTYPER_OT15_Pos (15U)
7954 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
7955 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7956 
7957 /* Legacy defines */
7958 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7959 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7960 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7961 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7962 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7963 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7964 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7965 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7966 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7967 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7968 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7969 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7970 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7971 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7972 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7973 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7974 
7975 /****************** Bits definition for GPIO_OSPEEDR register ***************/
7976 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7977 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
7978 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7979 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
7980 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
7981 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7982 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
7983 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7984 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
7985 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
7986 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7987 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
7988 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7989 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
7990 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
7991 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7992 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
7993 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7994 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
7995 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
7996 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7997 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
7998 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7999 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
8000 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
8001 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8002 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
8003 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8004 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
8005 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
8006 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8007 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
8008 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8009 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
8010 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
8011 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8012 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
8013 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8014 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
8015 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
8016 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8017 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
8018 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8019 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
8020 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
8021 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8022 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
8023 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8024 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
8025 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
8026 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8027 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
8028 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8029 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
8030 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
8031 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8032 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
8033 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8034 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
8035 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
8036 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8037 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
8038 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8039 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
8040 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
8041 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8042 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
8043 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8044 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
8045 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
8046 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8047 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
8048 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8049 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
8050 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
8051 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8052 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
8053 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8054 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
8055 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
8057 /* Legacy defines */
8058 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8059 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8060 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8061 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8062 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8063 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8064 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8065 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8066 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8067 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8068 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8069 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8070 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8071 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8072 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8073 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8074 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8075 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8076 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8077 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8078 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8079 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8080 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8081 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8082 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8083 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8084 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8085 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8086 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8087 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8088 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8089 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8090 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8091 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8092 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8093 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8094 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8095 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8096 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8097 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8098 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8099 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8100 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8101 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8102 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8103 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8104 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8105 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8106 
8107 /****************** Bits definition for GPIO_PUPDR register *****************/
8108 #define GPIO_PUPDR_PUPD0_Pos (0U)
8109 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
8110 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8111 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
8112 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
8113 #define GPIO_PUPDR_PUPD1_Pos (2U)
8114 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
8115 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8116 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
8117 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
8118 #define GPIO_PUPDR_PUPD2_Pos (4U)
8119 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
8120 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8121 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
8122 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
8123 #define GPIO_PUPDR_PUPD3_Pos (6U)
8124 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
8125 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8126 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
8127 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
8128 #define GPIO_PUPDR_PUPD4_Pos (8U)
8129 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
8130 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8131 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
8132 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
8133 #define GPIO_PUPDR_PUPD5_Pos (10U)
8134 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
8135 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8136 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
8137 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
8138 #define GPIO_PUPDR_PUPD6_Pos (12U)
8139 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
8140 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8141 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
8142 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
8143 #define GPIO_PUPDR_PUPD7_Pos (14U)
8144 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
8145 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8146 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
8147 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
8148 #define GPIO_PUPDR_PUPD8_Pos (16U)
8149 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
8150 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8151 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
8152 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
8153 #define GPIO_PUPDR_PUPD9_Pos (18U)
8154 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
8155 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8156 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8157 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8158 #define GPIO_PUPDR_PUPD10_Pos (20U)
8159 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8160 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8161 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8162 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8163 #define GPIO_PUPDR_PUPD11_Pos (22U)
8164 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8165 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8166 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8167 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8168 #define GPIO_PUPDR_PUPD12_Pos (24U)
8169 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8170 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8171 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8172 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8173 #define GPIO_PUPDR_PUPD13_Pos (26U)
8174 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8175 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8176 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8177 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8178 #define GPIO_PUPDR_PUPD14_Pos (28U)
8179 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8180 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8181 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8182 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8183 #define GPIO_PUPDR_PUPD15_Pos (30U)
8184 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8185 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8186 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8187 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8189 /* Legacy defines */
8190 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8191 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8192 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8193 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8194 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8195 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8196 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8197 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8198 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8199 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8200 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8201 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8202 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8203 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8204 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8205 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8206 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8207 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8208 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8209 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8210 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8211 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8212 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8213 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8214 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8215 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8216 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8217 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8218 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8219 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8220 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8221 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8222 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8223 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8224 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8225 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8226 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8227 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8228 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8229 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8230 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8231 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8232 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8233 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8234 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8235 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8236 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8237 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8238 
8239 /****************** Bits definition for GPIO_IDR register *******************/
8240 #define GPIO_IDR_ID0_Pos (0U)
8241 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8242 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8243 #define GPIO_IDR_ID1_Pos (1U)
8244 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8245 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8246 #define GPIO_IDR_ID2_Pos (2U)
8247 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8248 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8249 #define GPIO_IDR_ID3_Pos (3U)
8250 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8251 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8252 #define GPIO_IDR_ID4_Pos (4U)
8253 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8254 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8255 #define GPIO_IDR_ID5_Pos (5U)
8256 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8257 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8258 #define GPIO_IDR_ID6_Pos (6U)
8259 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8260 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8261 #define GPIO_IDR_ID7_Pos (7U)
8262 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8263 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8264 #define GPIO_IDR_ID8_Pos (8U)
8265 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8266 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8267 #define GPIO_IDR_ID9_Pos (9U)
8268 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8269 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8270 #define GPIO_IDR_ID10_Pos (10U)
8271 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8272 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8273 #define GPIO_IDR_ID11_Pos (11U)
8274 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8275 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8276 #define GPIO_IDR_ID12_Pos (12U)
8277 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8278 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8279 #define GPIO_IDR_ID13_Pos (13U)
8280 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8281 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8282 #define GPIO_IDR_ID14_Pos (14U)
8283 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8284 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8285 #define GPIO_IDR_ID15_Pos (15U)
8286 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8287 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8288 
8289 /* Legacy defines */
8290 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8291 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8292 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8293 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8294 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8295 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8296 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8297 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8298 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8299 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8300 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8301 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8302 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8303 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8304 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8305 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8306 
8307 /****************** Bits definition for GPIO_ODR register *******************/
8308 #define GPIO_ODR_OD0_Pos (0U)
8309 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8310 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8311 #define GPIO_ODR_OD1_Pos (1U)
8312 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8313 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8314 #define GPIO_ODR_OD2_Pos (2U)
8315 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8316 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8317 #define GPIO_ODR_OD3_Pos (3U)
8318 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8319 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8320 #define GPIO_ODR_OD4_Pos (4U)
8321 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8322 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8323 #define GPIO_ODR_OD5_Pos (5U)
8324 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8325 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8326 #define GPIO_ODR_OD6_Pos (6U)
8327 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8328 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8329 #define GPIO_ODR_OD7_Pos (7U)
8330 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8331 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8332 #define GPIO_ODR_OD8_Pos (8U)
8333 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8334 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8335 #define GPIO_ODR_OD9_Pos (9U)
8336 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8337 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8338 #define GPIO_ODR_OD10_Pos (10U)
8339 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8340 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8341 #define GPIO_ODR_OD11_Pos (11U)
8342 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8343 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8344 #define GPIO_ODR_OD12_Pos (12U)
8345 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8346 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8347 #define GPIO_ODR_OD13_Pos (13U)
8348 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8349 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8350 #define GPIO_ODR_OD14_Pos (14U)
8351 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8352 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8353 #define GPIO_ODR_OD15_Pos (15U)
8354 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8355 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8356 /* Legacy defines */
8357 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8358 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8359 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8360 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8361 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8362 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8363 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8364 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8365 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8366 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8367 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8368 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8369 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8370 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8371 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8372 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8373 
8374 /****************** Bits definition for GPIO_BSRR register ******************/
8375 #define GPIO_BSRR_BS0_Pos (0U)
8376 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8377 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8378 #define GPIO_BSRR_BS1_Pos (1U)
8379 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8380 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8381 #define GPIO_BSRR_BS2_Pos (2U)
8382 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8383 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8384 #define GPIO_BSRR_BS3_Pos (3U)
8385 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8386 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8387 #define GPIO_BSRR_BS4_Pos (4U)
8388 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8389 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8390 #define GPIO_BSRR_BS5_Pos (5U)
8391 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8392 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8393 #define GPIO_BSRR_BS6_Pos (6U)
8394 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8395 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8396 #define GPIO_BSRR_BS7_Pos (7U)
8397 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8398 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8399 #define GPIO_BSRR_BS8_Pos (8U)
8400 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8401 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8402 #define GPIO_BSRR_BS9_Pos (9U)
8403 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8404 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8405 #define GPIO_BSRR_BS10_Pos (10U)
8406 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8407 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8408 #define GPIO_BSRR_BS11_Pos (11U)
8409 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8410 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8411 #define GPIO_BSRR_BS12_Pos (12U)
8412 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8413 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8414 #define GPIO_BSRR_BS13_Pos (13U)
8415 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8416 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8417 #define GPIO_BSRR_BS14_Pos (14U)
8418 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8419 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8420 #define GPIO_BSRR_BS15_Pos (15U)
8421 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8422 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8423 #define GPIO_BSRR_BR0_Pos (16U)
8424 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8425 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8426 #define GPIO_BSRR_BR1_Pos (17U)
8427 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8428 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8429 #define GPIO_BSRR_BR2_Pos (18U)
8430 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8431 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8432 #define GPIO_BSRR_BR3_Pos (19U)
8433 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8434 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8435 #define GPIO_BSRR_BR4_Pos (20U)
8436 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8437 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8438 #define GPIO_BSRR_BR5_Pos (21U)
8439 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8440 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8441 #define GPIO_BSRR_BR6_Pos (22U)
8442 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8443 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8444 #define GPIO_BSRR_BR7_Pos (23U)
8445 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8446 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8447 #define GPIO_BSRR_BR8_Pos (24U)
8448 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8449 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8450 #define GPIO_BSRR_BR9_Pos (25U)
8451 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8452 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8453 #define GPIO_BSRR_BR10_Pos (26U)
8454 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8455 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8456 #define GPIO_BSRR_BR11_Pos (27U)
8457 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8458 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8459 #define GPIO_BSRR_BR12_Pos (28U)
8460 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8461 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8462 #define GPIO_BSRR_BR13_Pos (29U)
8463 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8464 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8465 #define GPIO_BSRR_BR14_Pos (30U)
8466 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8467 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8468 #define GPIO_BSRR_BR15_Pos (31U)
8469 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8470 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8471 
8472 /* Legacy defines */
8473 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8474 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8475 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8476 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8477 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8478 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8479 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8480 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8481 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8482 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8483 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8484 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8485 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8486 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8487 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8488 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8489 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8490 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8491 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8492 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8493 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8494 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8495 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8496 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8497 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8498 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8499 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8500 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8501 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8502 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8503 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8504 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8505 #define GPIO_BRR_BR0 GPIO_BSRR_BR0
8506 #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8507 #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8508 #define GPIO_BRR_BR1 GPIO_BSRR_BR1
8509 #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8510 #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8511 #define GPIO_BRR_BR2 GPIO_BSRR_BR2
8512 #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8513 #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8514 #define GPIO_BRR_BR3 GPIO_BSRR_BR3
8515 #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8516 #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8517 #define GPIO_BRR_BR4 GPIO_BSRR_BR4
8518 #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8519 #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8520 #define GPIO_BRR_BR5 GPIO_BSRR_BR5
8521 #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8522 #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8523 #define GPIO_BRR_BR6 GPIO_BSRR_BR6
8524 #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8525 #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8526 #define GPIO_BRR_BR7 GPIO_BSRR_BR7
8527 #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8528 #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8529 #define GPIO_BRR_BR8 GPIO_BSRR_BR8
8530 #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8531 #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8532 #define GPIO_BRR_BR9 GPIO_BSRR_BR9
8533 #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8534 #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8535 #define GPIO_BRR_BR10 GPIO_BSRR_BR10
8536 #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8537 #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8538 #define GPIO_BRR_BR11 GPIO_BSRR_BR11
8539 #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8540 #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8541 #define GPIO_BRR_BR12 GPIO_BSRR_BR12
8542 #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8543 #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8544 #define GPIO_BRR_BR13 GPIO_BSRR_BR13
8545 #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8546 #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8547 #define GPIO_BRR_BR14 GPIO_BSRR_BR14
8548 #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8549 #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8550 #define GPIO_BRR_BR15 GPIO_BSRR_BR15
8551 #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8552 #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8553 /****************** Bit definition for GPIO_LCKR register *********************/
8554 #define GPIO_LCKR_LCK0_Pos (0U)
8555 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8556 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8557 #define GPIO_LCKR_LCK1_Pos (1U)
8558 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8559 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8560 #define GPIO_LCKR_LCK2_Pos (2U)
8561 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8562 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8563 #define GPIO_LCKR_LCK3_Pos (3U)
8564 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8565 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8566 #define GPIO_LCKR_LCK4_Pos (4U)
8567 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8568 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8569 #define GPIO_LCKR_LCK5_Pos (5U)
8570 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8571 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8572 #define GPIO_LCKR_LCK6_Pos (6U)
8573 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8574 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8575 #define GPIO_LCKR_LCK7_Pos (7U)
8576 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8577 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8578 #define GPIO_LCKR_LCK8_Pos (8U)
8579 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8580 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8581 #define GPIO_LCKR_LCK9_Pos (9U)
8582 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8583 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8584 #define GPIO_LCKR_LCK10_Pos (10U)
8585 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8586 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8587 #define GPIO_LCKR_LCK11_Pos (11U)
8588 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8589 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8590 #define GPIO_LCKR_LCK12_Pos (12U)
8591 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8592 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8593 #define GPIO_LCKR_LCK13_Pos (13U)
8594 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8595 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8596 #define GPIO_LCKR_LCK14_Pos (14U)
8597 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8598 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8599 #define GPIO_LCKR_LCK15_Pos (15U)
8600 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8601 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8602 #define GPIO_LCKR_LCKK_Pos (16U)
8603 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8604 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8605 /****************** Bit definition for GPIO_AFRL register *********************/
8606 #define GPIO_AFRL_AFSEL0_Pos (0U)
8607 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8608 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8609 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8610 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8611 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8612 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8613 #define GPIO_AFRL_AFSEL1_Pos (4U)
8614 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8615 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8616 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8617 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8618 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8619 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8620 #define GPIO_AFRL_AFSEL2_Pos (8U)
8621 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8622 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8623 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8624 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8625 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8626 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8627 #define GPIO_AFRL_AFSEL3_Pos (12U)
8628 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8629 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8630 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8631 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8632 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8633 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8634 #define GPIO_AFRL_AFSEL4_Pos (16U)
8635 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8636 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8637 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8638 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8639 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8640 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8641 #define GPIO_AFRL_AFSEL5_Pos (20U)
8642 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8643 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8644 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8645 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8646 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8647 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8648 #define GPIO_AFRL_AFSEL6_Pos (24U)
8649 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8650 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8651 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8652 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8653 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8654 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8655 #define GPIO_AFRL_AFSEL7_Pos (28U)
8656 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8657 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8658 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8659 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8660 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8661 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8663 /* Legacy defines */
8664 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8665 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8666 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8667 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8668 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8669 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8670 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8671 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8672 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8673 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8674 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8675 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8676 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8677 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8678 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8679 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8680 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8681 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8682 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8683 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8684 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8685 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8686 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8687 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8688 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8689 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8690 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8691 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8692 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8693 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8694 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8695 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8696 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8697 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8698 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8699 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8700 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8701 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8702 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8703 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8704 
8705 /****************** Bit definition for GPIO_AFRH register *********************/
8706 #define GPIO_AFRH_AFSEL8_Pos (0U)
8707 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
8708 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8709 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
8710 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
8711 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
8712 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
8713 #define GPIO_AFRH_AFSEL9_Pos (4U)
8714 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
8715 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8716 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
8717 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
8718 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
8719 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
8720 #define GPIO_AFRH_AFSEL10_Pos (8U)
8721 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
8722 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8723 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
8724 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
8725 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
8726 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
8727 #define GPIO_AFRH_AFSEL11_Pos (12U)
8728 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
8729 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8730 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
8731 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
8732 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
8733 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
8734 #define GPIO_AFRH_AFSEL12_Pos (16U)
8735 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
8736 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8737 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
8738 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
8739 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
8740 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
8741 #define GPIO_AFRH_AFSEL13_Pos (20U)
8742 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
8743 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8744 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
8745 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
8746 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
8747 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
8748 #define GPIO_AFRH_AFSEL14_Pos (24U)
8749 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
8750 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8751 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
8752 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
8753 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
8754 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
8755 #define GPIO_AFRH_AFSEL15_Pos (28U)
8756 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
8757 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8758 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
8759 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
8760 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
8761 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
8763 /* Legacy defines */
8764 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8765 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8766 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8767 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8768 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8769 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8770 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8771 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8772 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8773 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8774 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8775 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8776 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8777 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8778 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8779 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8780 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8781 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8782 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8783 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8784 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8785 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8786 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8787 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8788 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8789 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8790 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8791 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8792 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8793 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8794 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8795 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8796 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8797 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8798 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8799 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8800 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8801 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8802 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8803 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8804 
8805 
8806 /******************************************************************************/
8807 /* */
8808 /* Inter-integrated Circuit Interface */
8809 /* */
8810 /******************************************************************************/
8811 /******************* Bit definition for I2C_CR1 register ********************/
8812 #define I2C_CR1_PE_Pos (0U)
8813 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8814 #define I2C_CR1_PE I2C_CR1_PE_Msk
8815 #define I2C_CR1_SMBUS_Pos (1U)
8816 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
8817 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
8818 #define I2C_CR1_SMBTYPE_Pos (3U)
8819 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
8820 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
8821 #define I2C_CR1_ENARP_Pos (4U)
8822 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
8823 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
8824 #define I2C_CR1_ENPEC_Pos (5U)
8825 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
8826 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
8827 #define I2C_CR1_ENGC_Pos (6U)
8828 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
8829 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
8830 #define I2C_CR1_NOSTRETCH_Pos (7U)
8831 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8832 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8833 #define I2C_CR1_START_Pos (8U)
8834 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
8835 #define I2C_CR1_START I2C_CR1_START_Msk
8836 #define I2C_CR1_STOP_Pos (9U)
8837 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
8838 #define I2C_CR1_STOP I2C_CR1_STOP_Msk
8839 #define I2C_CR1_ACK_Pos (10U)
8840 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
8841 #define I2C_CR1_ACK I2C_CR1_ACK_Msk
8842 #define I2C_CR1_POS_Pos (11U)
8843 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
8844 #define I2C_CR1_POS I2C_CR1_POS_Msk
8845 #define I2C_CR1_PEC_Pos (12U)
8846 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
8847 #define I2C_CR1_PEC I2C_CR1_PEC_Msk
8848 #define I2C_CR1_ALERT_Pos (13U)
8849 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
8850 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
8851 #define I2C_CR1_SWRST_Pos (15U)
8852 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
8853 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
8855 /******************* Bit definition for I2C_CR2 register ********************/
8856 #define I2C_CR2_FREQ_Pos (0U)
8857 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
8858 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
8859 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
8860 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
8861 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
8862 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
8863 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
8864 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
8866 #define I2C_CR2_ITERREN_Pos (8U)
8867 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
8868 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
8869 #define I2C_CR2_ITEVTEN_Pos (9U)
8870 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
8871 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
8872 #define I2C_CR2_ITBUFEN_Pos (10U)
8873 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
8874 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
8875 #define I2C_CR2_DMAEN_Pos (11U)
8876 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
8877 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
8878 #define I2C_CR2_LAST_Pos (12U)
8879 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
8880 #define I2C_CR2_LAST I2C_CR2_LAST_Msk
8882 /******************* Bit definition for I2C_OAR1 register *******************/
8883 #define I2C_OAR1_ADD1_7 0x000000FEU
8884 #define I2C_OAR1_ADD8_9 0x00000300U
8886 #define I2C_OAR1_ADD0_Pos (0U)
8887 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
8888 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
8889 #define I2C_OAR1_ADD1_Pos (1U)
8890 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
8891 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
8892 #define I2C_OAR1_ADD2_Pos (2U)
8893 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
8894 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
8895 #define I2C_OAR1_ADD3_Pos (3U)
8896 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
8897 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
8898 #define I2C_OAR1_ADD4_Pos (4U)
8899 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
8900 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
8901 #define I2C_OAR1_ADD5_Pos (5U)
8902 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
8903 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
8904 #define I2C_OAR1_ADD6_Pos (6U)
8905 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
8906 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
8907 #define I2C_OAR1_ADD7_Pos (7U)
8908 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
8909 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
8910 #define I2C_OAR1_ADD8_Pos (8U)
8911 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
8912 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
8913 #define I2C_OAR1_ADD9_Pos (9U)
8914 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
8915 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
8917 #define I2C_OAR1_ADDMODE_Pos (15U)
8918 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
8919 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
8921 /******************* Bit definition for I2C_OAR2 register *******************/
8922 #define I2C_OAR2_ENDUAL_Pos (0U)
8923 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
8924 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
8925 #define I2C_OAR2_ADD2_Pos (1U)
8926 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
8927 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
8929 /******************** Bit definition for I2C_DR register ********************/
8930 #define I2C_DR_DR_Pos (0U)
8931 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
8932 #define I2C_DR_DR I2C_DR_DR_Msk
8934 /******************* Bit definition for I2C_SR1 register ********************/
8935 #define I2C_SR1_SB_Pos (0U)
8936 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
8937 #define I2C_SR1_SB I2C_SR1_SB_Msk
8938 #define I2C_SR1_ADDR_Pos (1U)
8939 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
8940 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
8941 #define I2C_SR1_BTF_Pos (2U)
8942 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
8943 #define I2C_SR1_BTF I2C_SR1_BTF_Msk
8944 #define I2C_SR1_ADD10_Pos (3U)
8945 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
8946 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
8947 #define I2C_SR1_STOPF_Pos (4U)
8948 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
8949 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
8950 #define I2C_SR1_RXNE_Pos (6U)
8951 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
8952 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
8953 #define I2C_SR1_TXE_Pos (7U)
8954 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
8955 #define I2C_SR1_TXE I2C_SR1_TXE_Msk
8956 #define I2C_SR1_BERR_Pos (8U)
8957 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
8958 #define I2C_SR1_BERR I2C_SR1_BERR_Msk
8959 #define I2C_SR1_ARLO_Pos (9U)
8960 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
8961 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
8962 #define I2C_SR1_AF_Pos (10U)
8963 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
8964 #define I2C_SR1_AF I2C_SR1_AF_Msk
8965 #define I2C_SR1_OVR_Pos (11U)
8966 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
8967 #define I2C_SR1_OVR I2C_SR1_OVR_Msk
8968 #define I2C_SR1_PECERR_Pos (12U)
8969 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
8970 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
8971 #define I2C_SR1_TIMEOUT_Pos (14U)
8972 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
8973 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
8974 #define I2C_SR1_SMBALERT_Pos (15U)
8975 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
8976 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
8978 /******************* Bit definition for I2C_SR2 register ********************/
8979 #define I2C_SR2_MSL_Pos (0U)
8980 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
8981 #define I2C_SR2_MSL I2C_SR2_MSL_Msk
8982 #define I2C_SR2_BUSY_Pos (1U)
8983 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
8984 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
8985 #define I2C_SR2_TRA_Pos (2U)
8986 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
8987 #define I2C_SR2_TRA I2C_SR2_TRA_Msk
8988 #define I2C_SR2_GENCALL_Pos (4U)
8989 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
8990 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
8991 #define I2C_SR2_SMBDEFAULT_Pos (5U)
8992 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
8993 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
8994 #define I2C_SR2_SMBHOST_Pos (6U)
8995 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
8996 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
8997 #define I2C_SR2_DUALF_Pos (7U)
8998 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
8999 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
9000 #define I2C_SR2_PEC_Pos (8U)
9001 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
9002 #define I2C_SR2_PEC I2C_SR2_PEC_Msk
9004 /******************* Bit definition for I2C_CCR register ********************/
9005 #define I2C_CCR_CCR_Pos (0U)
9006 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
9007 #define I2C_CCR_CCR I2C_CCR_CCR_Msk
9008 #define I2C_CCR_DUTY_Pos (14U)
9009 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
9010 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
9011 #define I2C_CCR_FS_Pos (15U)
9012 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
9013 #define I2C_CCR_FS I2C_CCR_FS_Msk
9015 /****************** Bit definition for I2C_TRISE register *******************/
9016 #define I2C_TRISE_TRISE_Pos (0U)
9017 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
9018 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
9021 /******************************************************************************/
9022 /* */
9023 /* Independent WATCHDOG */
9024 /* */
9025 /******************************************************************************/
9026 /******************* Bit definition for IWDG_KR register ********************/
9027 #define IWDG_KR_KEY_Pos (0U)
9028 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9029 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
9031 /******************* Bit definition for IWDG_PR register ********************/
9032 #define IWDG_PR_PR_Pos (0U)
9033 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9034 #define IWDG_PR_PR IWDG_PR_PR_Msk
9035 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9036 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9037 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9039 /******************* Bit definition for IWDG_RLR register *******************/
9040 #define IWDG_RLR_RL_Pos (0U)
9041 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9042 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
9044 /******************* Bit definition for IWDG_SR register ********************/
9045 #define IWDG_SR_PVU_Pos (0U)
9046 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9047 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
9048 #define IWDG_SR_RVU_Pos (1U)
9049 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9050 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
9054 /******************************************************************************/
9055 /* */
9056 /* Power Control */
9057 /* */
9058 /******************************************************************************/
9059 /******************** Bit definition for PWR_CR register ********************/
9060 #define PWR_CR_LPDS_Pos (0U)
9061 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
9062 #define PWR_CR_LPDS PWR_CR_LPDS_Msk
9063 #define PWR_CR_PDDS_Pos (1U)
9064 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
9065 #define PWR_CR_PDDS PWR_CR_PDDS_Msk
9066 #define PWR_CR_CWUF_Pos (2U)
9067 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
9068 #define PWR_CR_CWUF PWR_CR_CWUF_Msk
9069 #define PWR_CR_CSBF_Pos (3U)
9070 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
9071 #define PWR_CR_CSBF PWR_CR_CSBF_Msk
9072 #define PWR_CR_PVDE_Pos (4U)
9073 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
9074 #define PWR_CR_PVDE PWR_CR_PVDE_Msk
9076 #define PWR_CR_PLS_Pos (5U)
9077 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
9078 #define PWR_CR_PLS PWR_CR_PLS_Msk
9079 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9080 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9081 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9084 #define PWR_CR_PLS_LEV0 0x00000000U
9085 #define PWR_CR_PLS_LEV1 0x00000020U
9086 #define PWR_CR_PLS_LEV2 0x00000040U
9087 #define PWR_CR_PLS_LEV3 0x00000060U
9088 #define PWR_CR_PLS_LEV4 0x00000080U
9089 #define PWR_CR_PLS_LEV5 0x000000A0U
9090 #define PWR_CR_PLS_LEV6 0x000000C0U
9091 #define PWR_CR_PLS_LEV7 0x000000E0U
9092 #define PWR_CR_DBP_Pos (8U)
9093 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9094 #define PWR_CR_DBP PWR_CR_DBP_Msk
9095 #define PWR_CR_FPDS_Pos (9U)
9096 #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9097 #define PWR_CR_FPDS PWR_CR_FPDS_Msk
9098 #define PWR_CR_VOS_Pos (14U)
9099 #define PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos)
9100 #define PWR_CR_VOS PWR_CR_VOS_Msk
9102 /* Legacy define */
9103 #define PWR_CR_PMODE PWR_CR_VOS
9104 
9105 /******************* Bit definition for PWR_CSR register ********************/
9106 #define PWR_CSR_WUF_Pos (0U)
9107 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9108 #define PWR_CSR_WUF PWR_CSR_WUF_Msk
9109 #define PWR_CSR_SBF_Pos (1U)
9110 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9111 #define PWR_CSR_SBF PWR_CSR_SBF_Msk
9112 #define PWR_CSR_PVDO_Pos (2U)
9113 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9114 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9115 #define PWR_CSR_BRR_Pos (3U)
9116 #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9117 #define PWR_CSR_BRR PWR_CSR_BRR_Msk
9118 #define PWR_CSR_EWUP_Pos (8U)
9119 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
9120 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
9121 #define PWR_CSR_BRE_Pos (9U)
9122 #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9123 #define PWR_CSR_BRE PWR_CSR_BRE_Msk
9124 #define PWR_CSR_VOSRDY_Pos (14U)
9125 #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
9126 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
9128 /* Legacy define */
9129 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9130 
9131 /******************************************************************************/
9132 /* */
9133 /* Reset and Clock Control */
9134 /* */
9135 /******************************************************************************/
9136 /******************** Bit definition for RCC_CR register ********************/
9137 #define RCC_CR_HSION_Pos (0U)
9138 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9139 #define RCC_CR_HSION RCC_CR_HSION_Msk
9140 #define RCC_CR_HSIRDY_Pos (1U)
9141 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9142 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9143 
9144 #define RCC_CR_HSITRIM_Pos (3U)
9145 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9146 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9147 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9148 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9149 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9150 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9151 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9153 #define RCC_CR_HSICAL_Pos (8U)
9154 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9155 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9156 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9157 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9158 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9159 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9160 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9161 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9162 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9163 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9165 #define RCC_CR_HSEON_Pos (16U)
9166 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9167 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
9168 #define RCC_CR_HSERDY_Pos (17U)
9169 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9170 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9171 #define RCC_CR_HSEBYP_Pos (18U)
9172 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9173 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9174 #define RCC_CR_CSSON_Pos (19U)
9175 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9176 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
9177 #define RCC_CR_PLLON_Pos (24U)
9178 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9179 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
9180 #define RCC_CR_PLLRDY_Pos (25U)
9181 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9182 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9183 /*
9184  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9185  */
9186 #define RCC_PLLI2S_SUPPORT
9188 #define RCC_CR_PLLI2SON_Pos (26U)
9189 #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9190 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9191 #define RCC_CR_PLLI2SRDY_Pos (27U)
9192 #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9193 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9194 
9195 /******************** Bit definition for RCC_PLLCFGR register ***************/
9196 #define RCC_PLLCFGR_PLLM_Pos (0U)
9197 #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9198 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9199 #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9200 #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9201 #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9202 #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9203 #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9204 #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9206 #define RCC_PLLCFGR_PLLN_Pos (6U)
9207 #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9208 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9209 #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9210 #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9211 #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9212 #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9213 #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9214 #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9215 #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9216 #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9217 #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9219 #define RCC_PLLCFGR_PLLP_Pos (16U)
9220 #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9221 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9222 #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9223 #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9225 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
9226 #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9227 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9228 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9229 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9230 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9231 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9232 
9233 #define RCC_PLLCFGR_PLLQ_Pos (24U)
9234 #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9235 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9236 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9237 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9238 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9239 #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9242 /******************** Bit definition for RCC_CFGR register ******************/
9244 #define RCC_CFGR_SW_Pos (0U)
9245 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9246 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
9247 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9248 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9250 #define RCC_CFGR_SW_HSI 0x00000000U
9251 #define RCC_CFGR_SW_HSE 0x00000001U
9252 #define RCC_CFGR_SW_PLL 0x00000002U
9255 #define RCC_CFGR_SWS_Pos (2U)
9256 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9257 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9258 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9259 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9261 #define RCC_CFGR_SWS_HSI 0x00000000U
9262 #define RCC_CFGR_SWS_HSE 0x00000004U
9263 #define RCC_CFGR_SWS_PLL 0x00000008U
9266 #define RCC_CFGR_HPRE_Pos (4U)
9267 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9268 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9269 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9270 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9271 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9272 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9274 #define RCC_CFGR_HPRE_DIV1 0x00000000U
9275 #define RCC_CFGR_HPRE_DIV2 0x00000080U
9276 #define RCC_CFGR_HPRE_DIV4 0x00000090U
9277 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
9278 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
9279 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
9280 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
9281 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
9282 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
9285 #define RCC_CFGR_PPRE1_Pos (10U)
9286 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9287 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9288 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9289 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9290 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9292 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
9293 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
9294 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
9295 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
9296 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9299 #define RCC_CFGR_PPRE2_Pos (13U)
9300 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9301 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9302 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9303 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9304 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9306 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
9307 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
9308 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9309 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9310 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9313 #define RCC_CFGR_RTCPRE_Pos (16U)
9314 #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9315 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9316 #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9317 #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9318 #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9319 #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9320 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9323 #define RCC_CFGR_MCO1_Pos (21U)
9324 #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9325 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9326 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9327 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9329 #define RCC_CFGR_I2SSRC_Pos (23U)
9330 #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
9331 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9332 
9333 #define RCC_CFGR_MCO1PRE_Pos (24U)
9334 #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9335 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9336 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9337 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9338 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9340 #define RCC_CFGR_MCO2PRE_Pos (27U)
9341 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9342 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9343 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9344 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9345 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9347 #define RCC_CFGR_MCO2_Pos (30U)
9348 #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9349 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9350 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9351 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9353 /******************** Bit definition for RCC_CIR register *******************/
9354 #define RCC_CIR_LSIRDYF_Pos (0U)
9355 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9356 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9357 #define RCC_CIR_LSERDYF_Pos (1U)
9358 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9359 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9360 #define RCC_CIR_HSIRDYF_Pos (2U)
9361 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9362 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9363 #define RCC_CIR_HSERDYF_Pos (3U)
9364 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9365 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9366 #define RCC_CIR_PLLRDYF_Pos (4U)
9367 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9368 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9369 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
9370 #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9371 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9372 
9373 #define RCC_CIR_CSSF_Pos (7U)
9374 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9375 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9376 #define RCC_CIR_LSIRDYIE_Pos (8U)
9377 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9378 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9379 #define RCC_CIR_LSERDYIE_Pos (9U)
9380 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9381 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9382 #define RCC_CIR_HSIRDYIE_Pos (10U)
9383 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9384 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9385 #define RCC_CIR_HSERDYIE_Pos (11U)
9386 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9387 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9388 #define RCC_CIR_PLLRDYIE_Pos (12U)
9389 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9390 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9391 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9392 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9393 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9394 
9395 #define RCC_CIR_LSIRDYC_Pos (16U)
9396 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9397 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9398 #define RCC_CIR_LSERDYC_Pos (17U)
9399 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9400 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9401 #define RCC_CIR_HSIRDYC_Pos (18U)
9402 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9403 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9404 #define RCC_CIR_HSERDYC_Pos (19U)
9405 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9406 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9407 #define RCC_CIR_PLLRDYC_Pos (20U)
9408 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9409 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9410 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
9411 #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9412 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9413 
9414 #define RCC_CIR_CSSC_Pos (23U)
9415 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9416 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9417 
9418 /******************** Bit definition for RCC_AHB1RSTR register **************/
9419 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9420 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9421 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9422 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9423 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9424 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9425 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9426 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9427 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9428 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9429 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9430 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9431 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9432 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9433 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9434 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9435 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9436 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9437 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9438 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9439 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9440 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9441 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9442 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9443 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9444 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
9445 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9446 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
9447 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9448 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9449 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9450 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9451 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9452 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9453 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9454 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9455 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9456 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
9457 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9458 
9459 /******************** Bit definition for RCC_AHB2RSTR register **************/
9460 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
9461 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9462 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9463 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9464 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9465 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9466 /******************** Bit definition for RCC_AHB3RSTR register **************/
9467 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9468 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9469 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9470 
9471 
9472 /******************** Bit definition for RCC_APB1RSTR register **************/
9473 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
9474 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9475 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9476 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
9477 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9478 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9479 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
9480 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9481 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9482 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
9483 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9484 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9485 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
9486 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9487 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9488 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
9489 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9490 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9491 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
9492 #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9493 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9494 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
9495 #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9496 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9497 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
9498 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9499 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9500 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
9501 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9502 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9503 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
9504 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9505 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9506 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
9507 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9508 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9509 #define RCC_APB1RSTR_USART2RST_Pos (17U)
9510 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9511 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9512 #define RCC_APB1RSTR_USART3RST_Pos (18U)
9513 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9514 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9515 #define RCC_APB1RSTR_UART4RST_Pos (19U)
9516 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9517 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9518 #define RCC_APB1RSTR_UART5RST_Pos (20U)
9519 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9520 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9521 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
9522 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9523 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9524 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
9525 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9526 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9527 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
9528 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9529 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9530 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
9531 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9532 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9533 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
9534 #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9535 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9536 #define RCC_APB1RSTR_PWRRST_Pos (28U)
9537 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9538 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9539 #define RCC_APB1RSTR_DACRST_Pos (29U)
9540 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9541 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9542 
9543 /******************** Bit definition for RCC_APB2RSTR register **************/
9544 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
9545 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9546 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9547 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
9548 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9549 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9550 #define RCC_APB2RSTR_USART1RST_Pos (4U)
9551 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9552 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9553 #define RCC_APB2RSTR_USART6RST_Pos (5U)
9554 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9555 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9556 #define RCC_APB2RSTR_ADCRST_Pos (8U)
9557 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9558 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9559 #define RCC_APB2RSTR_SDIORST_Pos (11U)
9560 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9561 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9562 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
9563 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9564 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9565 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9566 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9567 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9568 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
9569 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9570 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9571 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
9572 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9573 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9574 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
9575 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9576 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9577 
9578 /* Old SPI1RST bit definition, maintained for legacy purpose */
9579 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
9580 
9581 /******************** Bit definition for RCC_AHB1ENR register ***************/
9582 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9583 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9584 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9585 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9586 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9587 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9588 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9589 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9590 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9591 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
9592 #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9593 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9594 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9595 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9596 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9597 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9598 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
9599 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9600 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9601 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
9602 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9603 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9604 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9605 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9606 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9607 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
9608 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9609 #define RCC_AHB1ENR_CRCEN_Pos (12U)
9610 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9611 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9612 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9613 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
9614 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9615 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
9616 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
9617 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
9618 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
9619 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9620 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9621 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
9622 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9623 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9624 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9625 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
9626 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9627 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9628 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
9629 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9630 /******************** Bit definition for RCC_AHB2ENR register ***************/
9631 /*
9632  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9633  */
9634 #define RCC_AHB2_SUPPORT
9636 #define RCC_AHB2ENR_RNGEN_Pos (6U)
9637 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9638 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9639 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9640 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9641 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9642 
9643 /******************** Bit definition for RCC_AHB3ENR register ***************/
9644 /*
9645  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9646  */
9647 #define RCC_AHB3_SUPPORT
9649 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
9650 #define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
9651 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9652 
9653 /******************** Bit definition for RCC_APB1ENR register ***************/
9654 #define RCC_APB1ENR_TIM2EN_Pos (0U)
9655 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
9656 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9657 #define RCC_APB1ENR_TIM3EN_Pos (1U)
9658 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
9659 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9660 #define RCC_APB1ENR_TIM4EN_Pos (2U)
9661 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
9662 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9663 #define RCC_APB1ENR_TIM5EN_Pos (3U)
9664 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
9665 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9666 #define RCC_APB1ENR_TIM6EN_Pos (4U)
9667 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
9668 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9669 #define RCC_APB1ENR_TIM7EN_Pos (5U)
9670 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
9671 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9672 #define RCC_APB1ENR_TIM12EN_Pos (6U)
9673 #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
9674 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9675 #define RCC_APB1ENR_TIM13EN_Pos (7U)
9676 #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
9677 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9678 #define RCC_APB1ENR_TIM14EN_Pos (8U)
9679 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
9680 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9681 #define RCC_APB1ENR_WWDGEN_Pos (11U)
9682 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
9683 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9684 #define RCC_APB1ENR_SPI2EN_Pos (14U)
9685 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
9686 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9687 #define RCC_APB1ENR_SPI3EN_Pos (15U)
9688 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
9689 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
9690 #define RCC_APB1ENR_USART2EN_Pos (17U)
9691 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
9692 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
9693 #define RCC_APB1ENR_USART3EN_Pos (18U)
9694 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
9695 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
9696 #define RCC_APB1ENR_UART4EN_Pos (19U)
9697 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
9698 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
9699 #define RCC_APB1ENR_UART5EN_Pos (20U)
9700 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
9701 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
9702 #define RCC_APB1ENR_I2C1EN_Pos (21U)
9703 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
9704 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
9705 #define RCC_APB1ENR_I2C2EN_Pos (22U)
9706 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
9707 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
9708 #define RCC_APB1ENR_I2C3EN_Pos (23U)
9709 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
9710 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
9711 #define RCC_APB1ENR_CAN1EN_Pos (25U)
9712 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
9713 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
9714 #define RCC_APB1ENR_CAN2EN_Pos (26U)
9715 #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
9716 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
9717 #define RCC_APB1ENR_PWREN_Pos (28U)
9718 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
9719 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
9720 #define RCC_APB1ENR_DACEN_Pos (29U)
9721 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
9722 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
9723 
9724 /******************** Bit definition for RCC_APB2ENR register ***************/
9725 #define RCC_APB2ENR_TIM1EN_Pos (0U)
9726 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
9727 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9728 #define RCC_APB2ENR_TIM8EN_Pos (1U)
9729 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
9730 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
9731 #define RCC_APB2ENR_USART1EN_Pos (4U)
9732 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
9733 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9734 #define RCC_APB2ENR_USART6EN_Pos (5U)
9735 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
9736 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
9737 #define RCC_APB2ENR_ADC1EN_Pos (8U)
9738 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
9739 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
9740 #define RCC_APB2ENR_ADC2EN_Pos (9U)
9741 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
9742 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
9743 #define RCC_APB2ENR_ADC3EN_Pos (10U)
9744 #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
9745 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
9746 #define RCC_APB2ENR_SDIOEN_Pos (11U)
9747 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
9748 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
9749 #define RCC_APB2ENR_SPI1EN_Pos (12U)
9750 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
9751 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9752 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
9753 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
9754 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9755 #define RCC_APB2ENR_TIM9EN_Pos (16U)
9756 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
9757 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
9758 #define RCC_APB2ENR_TIM10EN_Pos (17U)
9759 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
9760 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
9761 #define RCC_APB2ENR_TIM11EN_Pos (18U)
9762 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
9763 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
9764 
9765 /******************** Bit definition for RCC_AHB1LPENR register *************/
9766 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
9767 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
9768 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
9769 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
9770 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
9771 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
9772 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
9773 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
9774 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
9775 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
9776 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
9777 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
9778 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
9779 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
9780 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
9781 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
9782 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
9783 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
9784 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
9785 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
9786 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
9787 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
9788 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
9789 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
9790 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
9791 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
9792 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
9793 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
9794 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
9795 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
9796 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
9797 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
9798 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
9799 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
9800 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
9801 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
9802 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
9803 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
9804 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
9805 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
9806 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
9807 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
9808 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
9809 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
9810 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
9811 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
9812 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
9813 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
9814 
9815 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
9816 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
9817 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
9818 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
9819 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
9820 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
9821 
9822 /******************** Bit definition for RCC_AHB2LPENR register *************/
9823 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
9824 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
9825 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
9826 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
9827 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
9828 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
9829 
9830 /******************** Bit definition for RCC_AHB3LPENR register *************/
9831 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
9832 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
9833 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
9834 
9835 /******************** Bit definition for RCC_APB1LPENR register *************/
9836 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
9837 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
9838 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
9839 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
9840 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
9841 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
9842 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
9843 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
9844 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
9845 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
9846 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
9847 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
9848 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
9849 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
9850 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
9851 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
9852 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
9853 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
9854 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
9855 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
9856 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
9857 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
9858 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
9859 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
9860 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
9861 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
9862 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
9863 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
9864 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
9865 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
9866 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
9867 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
9868 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
9869 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
9870 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
9871 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
9872 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
9873 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
9874 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
9875 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
9876 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
9877 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
9878 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
9879 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
9880 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
9881 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
9882 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
9883 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
9884 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
9885 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
9886 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
9887 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
9888 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
9889 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
9890 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
9891 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
9892 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
9893 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
9894 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
9895 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
9896 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
9897 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
9898 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
9899 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
9900 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
9901 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
9902 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
9903 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
9904 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
9905 
9906 /******************** Bit definition for RCC_APB2LPENR register *************/
9907 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
9908 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
9909 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
9910 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
9911 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
9912 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
9913 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
9914 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
9915 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
9916 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
9917 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
9918 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
9919 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
9920 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
9921 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
9922 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
9923 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
9924 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
9925 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
9926 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
9927 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
9928 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
9929 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
9930 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
9931 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
9932 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
9933 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
9934 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
9935 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
9936 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
9937 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
9938 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
9939 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
9940 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
9941 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
9942 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
9943 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
9944 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
9945 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
9946 
9947 /******************** Bit definition for RCC_BDCR register ******************/
9948 #define RCC_BDCR_LSEON_Pos (0U)
9949 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
9950 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
9951 #define RCC_BDCR_LSERDY_Pos (1U)
9952 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
9953 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
9954 #define RCC_BDCR_LSEBYP_Pos (2U)
9955 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
9956 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
9957 
9958 #define RCC_BDCR_RTCSEL_Pos (8U)
9959 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
9960 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
9961 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
9962 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
9964 #define RCC_BDCR_RTCEN_Pos (15U)
9965 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
9966 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
9967 #define RCC_BDCR_BDRST_Pos (16U)
9968 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
9969 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
9970 
9971 /******************** Bit definition for RCC_CSR register *******************/
9972 #define RCC_CSR_LSION_Pos (0U)
9973 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
9974 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
9975 #define RCC_CSR_LSIRDY_Pos (1U)
9976 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
9977 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
9978 #define RCC_CSR_RMVF_Pos (24U)
9979 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
9980 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
9981 #define RCC_CSR_BORRSTF_Pos (25U)
9982 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
9983 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
9984 #define RCC_CSR_PINRSTF_Pos (26U)
9985 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
9986 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
9987 #define RCC_CSR_PORRSTF_Pos (27U)
9988 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
9989 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
9990 #define RCC_CSR_SFTRSTF_Pos (28U)
9991 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
9992 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
9993 #define RCC_CSR_IWDGRSTF_Pos (29U)
9994 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
9995 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
9996 #define RCC_CSR_WWDGRSTF_Pos (30U)
9997 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
9998 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
9999 #define RCC_CSR_LPWRRSTF_Pos (31U)
10000 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10001 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10002 /* Legacy defines */
10003 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10004 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10005 
10006 /******************** Bit definition for RCC_SSCGR register *****************/
10007 #define RCC_SSCGR_MODPER_Pos (0U)
10008 #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10009 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10010 #define RCC_SSCGR_INCSTEP_Pos (13U)
10011 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10012 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10013 #define RCC_SSCGR_SPREADSEL_Pos (30U)
10014 #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10015 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10016 #define RCC_SSCGR_SSCGEN_Pos (31U)
10017 #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10018 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10019 
10020 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
10021 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10022 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10023 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10024 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10025 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10026 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10027 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10028 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10029 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10030 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10031 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10032 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10034 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10035 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10036 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10037 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10038 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10039 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10042 /******************************************************************************/
10043 /* */
10044 /* RNG */
10045 /* */
10046 /******************************************************************************/
10047 /******************** Bits definition for RNG_CR register *******************/
10048 #define RNG_CR_RNGEN_Pos (2U)
10049 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10050 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10051 #define RNG_CR_IE_Pos (3U)
10052 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10053 #define RNG_CR_IE RNG_CR_IE_Msk
10054 
10055 /******************** Bits definition for RNG_SR register *******************/
10056 #define RNG_SR_DRDY_Pos (0U)
10057 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10058 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
10059 #define RNG_SR_CECS_Pos (1U)
10060 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10061 #define RNG_SR_CECS RNG_SR_CECS_Msk
10062 #define RNG_SR_SECS_Pos (2U)
10063 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10064 #define RNG_SR_SECS RNG_SR_SECS_Msk
10065 #define RNG_SR_CEIS_Pos (5U)
10066 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10067 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
10068 #define RNG_SR_SEIS_Pos (6U)
10069 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10070 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
10071 
10072 /******************************************************************************/
10073 /* */
10074 /* Real-Time Clock (RTC) */
10075 /* */
10076 /******************************************************************************/
10077 /*
10078  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10079  */
10080 #define RTC_TAMPER2_SUPPORT
10081 #define RTC_AF2_SUPPORT
10082 /******************** Bits definition for RTC_TR register *******************/
10083 #define RTC_TR_PM_Pos (22U)
10084 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10085 #define RTC_TR_PM RTC_TR_PM_Msk
10086 #define RTC_TR_HT_Pos (20U)
10087 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10088 #define RTC_TR_HT RTC_TR_HT_Msk
10089 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10090 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10091 #define RTC_TR_HU_Pos (16U)
10092 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10093 #define RTC_TR_HU RTC_TR_HU_Msk
10094 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10095 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10096 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10097 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10098 #define RTC_TR_MNT_Pos (12U)
10099 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10100 #define RTC_TR_MNT RTC_TR_MNT_Msk
10101 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10102 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10103 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10104 #define RTC_TR_MNU_Pos (8U)
10105 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10106 #define RTC_TR_MNU RTC_TR_MNU_Msk
10107 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10108 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10109 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10110 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10111 #define RTC_TR_ST_Pos (4U)
10112 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10113 #define RTC_TR_ST RTC_TR_ST_Msk
10114 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10115 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10116 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10117 #define RTC_TR_SU_Pos (0U)
10118 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10119 #define RTC_TR_SU RTC_TR_SU_Msk
10120 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10121 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10122 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10123 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10125 /******************** Bits definition for RTC_DR register *******************/
10126 #define RTC_DR_YT_Pos (20U)
10127 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10128 #define RTC_DR_YT RTC_DR_YT_Msk
10129 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10130 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10131 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10132 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10133 #define RTC_DR_YU_Pos (16U)
10134 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10135 #define RTC_DR_YU RTC_DR_YU_Msk
10136 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10137 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10138 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10139 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10140 #define RTC_DR_WDU_Pos (13U)
10141 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10142 #define RTC_DR_WDU RTC_DR_WDU_Msk
10143 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10144 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10145 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10146 #define RTC_DR_MT_Pos (12U)
10147 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10148 #define RTC_DR_MT RTC_DR_MT_Msk
10149 #define RTC_DR_MU_Pos (8U)
10150 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10151 #define RTC_DR_MU RTC_DR_MU_Msk
10152 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10153 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10154 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10155 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10156 #define RTC_DR_DT_Pos (4U)
10157 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10158 #define RTC_DR_DT RTC_DR_DT_Msk
10159 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10160 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10161 #define RTC_DR_DU_Pos (0U)
10162 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10163 #define RTC_DR_DU RTC_DR_DU_Msk
10164 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10165 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10166 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10167 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10169 /******************** Bits definition for RTC_CR register *******************/
10170 #define RTC_CR_COE_Pos (23U)
10171 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10172 #define RTC_CR_COE RTC_CR_COE_Msk
10173 #define RTC_CR_OSEL_Pos (21U)
10174 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10175 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
10176 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10177 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10178 #define RTC_CR_POL_Pos (20U)
10179 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10180 #define RTC_CR_POL RTC_CR_POL_Msk
10181 #define RTC_CR_COSEL_Pos (19U)
10182 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10183 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
10184 #define RTC_CR_BKP_Pos (18U)
10185 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10186 #define RTC_CR_BKP RTC_CR_BKP_Msk
10187 #define RTC_CR_SUB1H_Pos (17U)
10188 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10189 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10190 #define RTC_CR_ADD1H_Pos (16U)
10191 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10192 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10193 #define RTC_CR_TSIE_Pos (15U)
10194 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10195 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
10196 #define RTC_CR_WUTIE_Pos (14U)
10197 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10198 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10199 #define RTC_CR_ALRBIE_Pos (13U)
10200 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10201 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10202 #define RTC_CR_ALRAIE_Pos (12U)
10203 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10204 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10205 #define RTC_CR_TSE_Pos (11U)
10206 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10207 #define RTC_CR_TSE RTC_CR_TSE_Msk
10208 #define RTC_CR_WUTE_Pos (10U)
10209 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10210 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
10211 #define RTC_CR_ALRBE_Pos (9U)
10212 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10213 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10214 #define RTC_CR_ALRAE_Pos (8U)
10215 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10216 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10217 #define RTC_CR_DCE_Pos (7U)
10218 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10219 #define RTC_CR_DCE RTC_CR_DCE_Msk
10220 #define RTC_CR_FMT_Pos (6U)
10221 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10222 #define RTC_CR_FMT RTC_CR_FMT_Msk
10223 #define RTC_CR_BYPSHAD_Pos (5U)
10224 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10225 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10226 #define RTC_CR_REFCKON_Pos (4U)
10227 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10228 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10229 #define RTC_CR_TSEDGE_Pos (3U)
10230 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10231 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10232 #define RTC_CR_WUCKSEL_Pos (0U)
10233 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10234 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10235 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10236 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10237 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10239 /* Legacy defines */
10240 #define RTC_CR_BCK RTC_CR_BKP
10241 
10242 /******************** Bits definition for RTC_ISR register ******************/
10243 #define RTC_ISR_RECALPF_Pos (16U)
10244 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10245 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10246 #define RTC_ISR_TAMP1F_Pos (13U)
10247 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10248 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10249 #define RTC_ISR_TAMP2F_Pos (14U)
10250 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10251 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10252 #define RTC_ISR_TSOVF_Pos (12U)
10253 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10254 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10255 #define RTC_ISR_TSF_Pos (11U)
10256 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10257 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
10258 #define RTC_ISR_WUTF_Pos (10U)
10259 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10260 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10261 #define RTC_ISR_ALRBF_Pos (9U)
10262 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10263 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10264 #define RTC_ISR_ALRAF_Pos (8U)
10265 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10266 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10267 #define RTC_ISR_INIT_Pos (7U)
10268 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10269 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
10270 #define RTC_ISR_INITF_Pos (6U)
10271 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10272 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
10273 #define RTC_ISR_RSF_Pos (5U)
10274 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10275 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
10276 #define RTC_ISR_INITS_Pos (4U)
10277 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10278 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
10279 #define RTC_ISR_SHPF_Pos (3U)
10280 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10281 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10282 #define RTC_ISR_WUTWF_Pos (2U)
10283 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10284 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10285 #define RTC_ISR_ALRBWF_Pos (1U)
10286 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10287 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10288 #define RTC_ISR_ALRAWF_Pos (0U)
10289 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10290 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10291 
10292 /******************** Bits definition for RTC_PRER register *****************/
10293 #define RTC_PRER_PREDIV_A_Pos (16U)
10294 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10295 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10296 #define RTC_PRER_PREDIV_S_Pos (0U)
10297 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10298 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10299 
10300 /******************** Bits definition for RTC_WUTR register *****************/
10301 #define RTC_WUTR_WUT_Pos (0U)
10302 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10303 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10304 
10305 /******************** Bits definition for RTC_CALIBR register ***************/
10306 #define RTC_CALIBR_DCS_Pos (7U)
10307 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10308 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10309 #define RTC_CALIBR_DC_Pos (0U)
10310 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10311 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10312 
10313 /******************** Bits definition for RTC_ALRMAR register ***************/
10314 #define RTC_ALRMAR_MSK4_Pos (31U)
10315 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10316 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10317 #define RTC_ALRMAR_WDSEL_Pos (30U)
10318 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10319 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10320 #define RTC_ALRMAR_DT_Pos (28U)
10321 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10322 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10323 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10324 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10325 #define RTC_ALRMAR_DU_Pos (24U)
10326 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10327 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10328 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10329 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10330 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10331 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10332 #define RTC_ALRMAR_MSK3_Pos (23U)
10333 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10334 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10335 #define RTC_ALRMAR_PM_Pos (22U)
10336 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10337 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10338 #define RTC_ALRMAR_HT_Pos (20U)
10339 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10340 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10341 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10342 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10343 #define RTC_ALRMAR_HU_Pos (16U)
10344 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10345 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10346 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10347 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10348 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10349 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10350 #define RTC_ALRMAR_MSK2_Pos (15U)
10351 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10352 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10353 #define RTC_ALRMAR_MNT_Pos (12U)
10354 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10355 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10356 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10357 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10358 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10359 #define RTC_ALRMAR_MNU_Pos (8U)
10360 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10361 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10362 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10363 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10364 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10365 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10366 #define RTC_ALRMAR_MSK1_Pos (7U)
10367 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10368 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10369 #define RTC_ALRMAR_ST_Pos (4U)
10370 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10371 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10372 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10373 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10374 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10375 #define RTC_ALRMAR_SU_Pos (0U)
10376 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10377 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10378 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10379 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10380 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10381 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10383 /******************** Bits definition for RTC_ALRMBR register ***************/
10384 #define RTC_ALRMBR_MSK4_Pos (31U)
10385 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10386 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10387 #define RTC_ALRMBR_WDSEL_Pos (30U)
10388 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10389 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10390 #define RTC_ALRMBR_DT_Pos (28U)
10391 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10392 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10393 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10394 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10395 #define RTC_ALRMBR_DU_Pos (24U)
10396 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10397 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10398 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10399 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10400 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10401 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10402 #define RTC_ALRMBR_MSK3_Pos (23U)
10403 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10404 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10405 #define RTC_ALRMBR_PM_Pos (22U)
10406 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10407 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10408 #define RTC_ALRMBR_HT_Pos (20U)
10409 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10410 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10411 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10412 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10413 #define RTC_ALRMBR_HU_Pos (16U)
10414 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10415 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10416 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10417 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10418 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10419 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10420 #define RTC_ALRMBR_MSK2_Pos (15U)
10421 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10422 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10423 #define RTC_ALRMBR_MNT_Pos (12U)
10424 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10425 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10426 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10427 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10428 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10429 #define RTC_ALRMBR_MNU_Pos (8U)
10430 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10431 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10432 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10433 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10434 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10435 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10436 #define RTC_ALRMBR_MSK1_Pos (7U)
10437 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10438 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10439 #define RTC_ALRMBR_ST_Pos (4U)
10440 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10441 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10442 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10443 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10444 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10445 #define RTC_ALRMBR_SU_Pos (0U)
10446 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10447 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10448 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10449 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10450 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10451 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10453 /******************** Bits definition for RTC_WPR register ******************/
10454 #define RTC_WPR_KEY_Pos (0U)
10455 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10456 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
10457 
10458 /******************** Bits definition for RTC_SSR register ******************/
10459 #define RTC_SSR_SS_Pos (0U)
10460 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10461 #define RTC_SSR_SS RTC_SSR_SS_Msk
10462 
10463 /******************** Bits definition for RTC_SHIFTR register ***************/
10464 #define RTC_SHIFTR_SUBFS_Pos (0U)
10465 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
10466 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10467 #define RTC_SHIFTR_ADD1S_Pos (31U)
10468 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
10469 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10470 
10471 /******************** Bits definition for RTC_TSTR register *****************/
10472 #define RTC_TSTR_PM_Pos (22U)
10473 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10474 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
10475 #define RTC_TSTR_HT_Pos (20U)
10476 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10477 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
10478 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10479 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10480 #define RTC_TSTR_HU_Pos (16U)
10481 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10482 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
10483 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10484 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10485 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10486 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10487 #define RTC_TSTR_MNT_Pos (12U)
10488 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10489 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10490 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10491 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10492 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10493 #define RTC_TSTR_MNU_Pos (8U)
10494 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10495 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10496 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10497 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10498 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10499 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10500 #define RTC_TSTR_ST_Pos (4U)
10501 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10502 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
10503 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10504 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10505 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10506 #define RTC_TSTR_SU_Pos (0U)
10507 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10508 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
10509 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10510 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10511 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10512 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10514 /******************** Bits definition for RTC_TSDR register *****************/
10515 #define RTC_TSDR_WDU_Pos (13U)
10516 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10517 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10518 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10519 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10520 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10521 #define RTC_TSDR_MT_Pos (12U)
10522 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10523 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
10524 #define RTC_TSDR_MU_Pos (8U)
10525 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10526 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
10527 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10528 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10529 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10530 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10531 #define RTC_TSDR_DT_Pos (4U)
10532 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10533 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
10534 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10535 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10536 #define RTC_TSDR_DU_Pos (0U)
10537 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10538 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
10539 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10540 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10541 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10542 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10544 /******************** Bits definition for RTC_TSSSR register ****************/
10545 #define RTC_TSSSR_SS_Pos (0U)
10546 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
10547 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10548 
10549 /******************** Bits definition for RTC_CAL register *****************/
10550 #define RTC_CALR_CALP_Pos (15U)
10551 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
10552 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
10553 #define RTC_CALR_CALW8_Pos (14U)
10554 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
10555 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10556 #define RTC_CALR_CALW16_Pos (13U)
10557 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
10558 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10559 #define RTC_CALR_CALM_Pos (0U)
10560 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
10561 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
10562 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
10563 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
10564 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
10565 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
10566 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
10567 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
10568 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
10569 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
10570 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
10572 /******************** Bits definition for RTC_TAFCR register ****************/
10573 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10574 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
10575 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10576 #define RTC_TAFCR_TSINSEL_Pos (17U)
10577 #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
10578 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10579 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10580 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
10581 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10582 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10583 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
10584 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10585 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
10586 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
10587 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10588 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
10589 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
10590 #define RTC_TAFCR_TAMPFLT_Pos (11U)
10591 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
10592 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10593 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
10594 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
10595 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
10596 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
10597 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10598 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
10599 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
10600 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
10601 #define RTC_TAFCR_TAMPTS_Pos (7U)
10602 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
10603 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10604 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
10605 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
10606 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10607 #define RTC_TAFCR_TAMP2E_Pos (3U)
10608 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
10609 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10610 #define RTC_TAFCR_TAMPIE_Pos (2U)
10611 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
10612 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10613 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
10614 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
10615 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10616 #define RTC_TAFCR_TAMP1E_Pos (0U)
10617 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
10618 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10619 
10620 /* Legacy defines */
10621 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10622 
10623 /******************** Bits definition for RTC_ALRMASSR register *************/
10624 #define RTC_ALRMASSR_MASKSS_Pos (24U)
10625 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
10626 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10627 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
10628 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
10629 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
10630 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
10631 #define RTC_ALRMASSR_SS_Pos (0U)
10632 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
10633 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10634 
10635 /******************** Bits definition for RTC_ALRMBSSR register *************/
10636 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
10637 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
10638 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10639 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
10640 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
10641 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
10642 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
10643 #define RTC_ALRMBSSR_SS_Pos (0U)
10644 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
10645 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10646 
10647 /******************** Bits definition for RTC_BKP0R register ****************/
10648 #define RTC_BKP0R_Pos (0U)
10649 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10650 #define RTC_BKP0R RTC_BKP0R_Msk
10651 
10652 /******************** Bits definition for RTC_BKP1R register ****************/
10653 #define RTC_BKP1R_Pos (0U)
10654 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10655 #define RTC_BKP1R RTC_BKP1R_Msk
10656 
10657 /******************** Bits definition for RTC_BKP2R register ****************/
10658 #define RTC_BKP2R_Pos (0U)
10659 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10660 #define RTC_BKP2R RTC_BKP2R_Msk
10661 
10662 /******************** Bits definition for RTC_BKP3R register ****************/
10663 #define RTC_BKP3R_Pos (0U)
10664 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
10665 #define RTC_BKP3R RTC_BKP3R_Msk
10666 
10667 /******************** Bits definition for RTC_BKP4R register ****************/
10668 #define RTC_BKP4R_Pos (0U)
10669 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
10670 #define RTC_BKP4R RTC_BKP4R_Msk
10671 
10672 /******************** Bits definition for RTC_BKP5R register ****************/
10673 #define RTC_BKP5R_Pos (0U)
10674 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
10675 #define RTC_BKP5R RTC_BKP5R_Msk
10676 
10677 /******************** Bits definition for RTC_BKP6R register ****************/
10678 #define RTC_BKP6R_Pos (0U)
10679 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
10680 #define RTC_BKP6R RTC_BKP6R_Msk
10681 
10682 /******************** Bits definition for RTC_BKP7R register ****************/
10683 #define RTC_BKP7R_Pos (0U)
10684 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
10685 #define RTC_BKP7R RTC_BKP7R_Msk
10686 
10687 /******************** Bits definition for RTC_BKP8R register ****************/
10688 #define RTC_BKP8R_Pos (0U)
10689 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
10690 #define RTC_BKP8R RTC_BKP8R_Msk
10691 
10692 /******************** Bits definition for RTC_BKP9R register ****************/
10693 #define RTC_BKP9R_Pos (0U)
10694 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
10695 #define RTC_BKP9R RTC_BKP9R_Msk
10696 
10697 /******************** Bits definition for RTC_BKP10R register ***************/
10698 #define RTC_BKP10R_Pos (0U)
10699 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
10700 #define RTC_BKP10R RTC_BKP10R_Msk
10701 
10702 /******************** Bits definition for RTC_BKP11R register ***************/
10703 #define RTC_BKP11R_Pos (0U)
10704 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
10705 #define RTC_BKP11R RTC_BKP11R_Msk
10706 
10707 /******************** Bits definition for RTC_BKP12R register ***************/
10708 #define RTC_BKP12R_Pos (0U)
10709 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
10710 #define RTC_BKP12R RTC_BKP12R_Msk
10711 
10712 /******************** Bits definition for RTC_BKP13R register ***************/
10713 #define RTC_BKP13R_Pos (0U)
10714 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
10715 #define RTC_BKP13R RTC_BKP13R_Msk
10716 
10717 /******************** Bits definition for RTC_BKP14R register ***************/
10718 #define RTC_BKP14R_Pos (0U)
10719 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
10720 #define RTC_BKP14R RTC_BKP14R_Msk
10721 
10722 /******************** Bits definition for RTC_BKP15R register ***************/
10723 #define RTC_BKP15R_Pos (0U)
10724 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
10725 #define RTC_BKP15R RTC_BKP15R_Msk
10726 
10727 /******************** Bits definition for RTC_BKP16R register ***************/
10728 #define RTC_BKP16R_Pos (0U)
10729 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
10730 #define RTC_BKP16R RTC_BKP16R_Msk
10731 
10732 /******************** Bits definition for RTC_BKP17R register ***************/
10733 #define RTC_BKP17R_Pos (0U)
10734 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
10735 #define RTC_BKP17R RTC_BKP17R_Msk
10736 
10737 /******************** Bits definition for RTC_BKP18R register ***************/
10738 #define RTC_BKP18R_Pos (0U)
10739 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
10740 #define RTC_BKP18R RTC_BKP18R_Msk
10741 
10742 /******************** Bits definition for RTC_BKP19R register ***************/
10743 #define RTC_BKP19R_Pos (0U)
10744 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
10745 #define RTC_BKP19R RTC_BKP19R_Msk
10746 
10747 /******************** Number of backup registers ******************************/
10748 #define RTC_BKP_NUMBER 0x000000014U
10749 
10750 
10751 /******************************************************************************/
10752 /* */
10753 /* SD host Interface */
10754 /* */
10755 /******************************************************************************/
10756 /****************** Bit definition for SDIO_POWER register ******************/
10757 #define SDIO_POWER_PWRCTRL_Pos (0U)
10758 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
10759 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
10760 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
10761 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
10763 /****************** Bit definition for SDIO_CLKCR register ******************/
10764 #define SDIO_CLKCR_CLKDIV_Pos (0U)
10765 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
10766 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
10767 #define SDIO_CLKCR_CLKEN_Pos (8U)
10768 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
10769 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
10770 #define SDIO_CLKCR_PWRSAV_Pos (9U)
10771 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
10772 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
10773 #define SDIO_CLKCR_BYPASS_Pos (10U)
10774 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
10775 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
10777 #define SDIO_CLKCR_WIDBUS_Pos (11U)
10778 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
10779 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
10780 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
10781 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
10783 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
10784 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
10785 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
10786 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
10787 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
10788 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
10790 /******************* Bit definition for SDIO_ARG register *******************/
10791 #define SDIO_ARG_CMDARG_Pos (0U)
10792 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
10793 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
10795 /******************* Bit definition for SDIO_CMD register *******************/
10796 #define SDIO_CMD_CMDINDEX_Pos (0U)
10797 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
10798 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
10800 #define SDIO_CMD_WAITRESP_Pos (6U)
10801 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
10802 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
10803 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
10804 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
10806 #define SDIO_CMD_WAITINT_Pos (8U)
10807 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
10808 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
10809 #define SDIO_CMD_WAITPEND_Pos (9U)
10810 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
10811 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
10812 #define SDIO_CMD_CPSMEN_Pos (10U)
10813 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
10814 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
10815 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
10816 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
10817 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
10818 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
10819 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
10820 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
10821 #define SDIO_CMD_NIEN_Pos (13U)
10822 #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
10823 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
10824 #define SDIO_CMD_CEATACMD_Pos (14U)
10825 #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
10826 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
10828 /***************** Bit definition for SDIO_RESPCMD register *****************/
10829 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
10830 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
10831 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
10833 /****************** Bit definition for SDIO_RESP0 register ******************/
10834 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
10835 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
10836 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
10838 /****************** Bit definition for SDIO_RESP1 register ******************/
10839 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
10840 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
10841 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
10843 /****************** Bit definition for SDIO_RESP2 register ******************/
10844 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
10845 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
10846 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
10848 /****************** Bit definition for SDIO_RESP3 register ******************/
10849 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
10850 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
10851 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
10853 /****************** Bit definition for SDIO_RESP4 register ******************/
10854 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
10855 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
10856 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
10858 /****************** Bit definition for SDIO_DTIMER register *****************/
10859 #define SDIO_DTIMER_DATATIME_Pos (0U)
10860 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
10861 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
10863 /****************** Bit definition for SDIO_DLEN register *******************/
10864 #define SDIO_DLEN_DATALENGTH_Pos (0U)
10865 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
10866 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
10868 /****************** Bit definition for SDIO_DCTRL register ******************/
10869 #define SDIO_DCTRL_DTEN_Pos (0U)
10870 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
10871 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
10872 #define SDIO_DCTRL_DTDIR_Pos (1U)
10873 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
10874 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
10875 #define SDIO_DCTRL_DTMODE_Pos (2U)
10876 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
10877 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
10878 #define SDIO_DCTRL_DMAEN_Pos (3U)
10879 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
10880 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
10882 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
10883 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10884 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
10885 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10886 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10887 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10888 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10890 #define SDIO_DCTRL_RWSTART_Pos (8U)
10891 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
10892 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
10893 #define SDIO_DCTRL_RWSTOP_Pos (9U)
10894 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
10895 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
10896 #define SDIO_DCTRL_RWMOD_Pos (10U)
10897 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
10898 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
10899 #define SDIO_DCTRL_SDIOEN_Pos (11U)
10900 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
10901 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
10903 /****************** Bit definition for SDIO_DCOUNT register *****************/
10904 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
10905 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
10906 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
10908 /****************** Bit definition for SDIO_STA register ********************/
10909 #define SDIO_STA_CCRCFAIL_Pos (0U)
10910 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
10911 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
10912 #define SDIO_STA_DCRCFAIL_Pos (1U)
10913 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
10914 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
10915 #define SDIO_STA_CTIMEOUT_Pos (2U)
10916 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
10917 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
10918 #define SDIO_STA_DTIMEOUT_Pos (3U)
10919 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
10920 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
10921 #define SDIO_STA_TXUNDERR_Pos (4U)
10922 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
10923 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
10924 #define SDIO_STA_RXOVERR_Pos (5U)
10925 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
10926 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
10927 #define SDIO_STA_CMDREND_Pos (6U)
10928 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
10929 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
10930 #define SDIO_STA_CMDSENT_Pos (7U)
10931 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
10932 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
10933 #define SDIO_STA_DATAEND_Pos (8U)
10934 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
10935 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
10936 #define SDIO_STA_STBITERR_Pos (9U)
10937 #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
10938 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
10939 #define SDIO_STA_DBCKEND_Pos (10U)
10940 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
10941 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
10942 #define SDIO_STA_CMDACT_Pos (11U)
10943 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
10944 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
10945 #define SDIO_STA_TXACT_Pos (12U)
10946 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
10947 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
10948 #define SDIO_STA_RXACT_Pos (13U)
10949 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
10950 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
10951 #define SDIO_STA_TXFIFOHE_Pos (14U)
10952 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
10953 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
10954 #define SDIO_STA_RXFIFOHF_Pos (15U)
10955 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
10956 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
10957 #define SDIO_STA_TXFIFOF_Pos (16U)
10958 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
10959 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
10960 #define SDIO_STA_RXFIFOF_Pos (17U)
10961 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
10962 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
10963 #define SDIO_STA_TXFIFOE_Pos (18U)
10964 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
10965 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
10966 #define SDIO_STA_RXFIFOE_Pos (19U)
10967 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
10968 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
10969 #define SDIO_STA_TXDAVL_Pos (20U)
10970 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
10971 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
10972 #define SDIO_STA_RXDAVL_Pos (21U)
10973 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
10974 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
10975 #define SDIO_STA_SDIOIT_Pos (22U)
10976 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
10977 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
10978 #define SDIO_STA_CEATAEND_Pos (23U)
10979 #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
10980 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
10982 /******************* Bit definition for SDIO_ICR register *******************/
10983 #define SDIO_ICR_CCRCFAILC_Pos (0U)
10984 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
10985 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
10986 #define SDIO_ICR_DCRCFAILC_Pos (1U)
10987 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
10988 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
10989 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
10990 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
10991 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
10992 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
10993 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
10994 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
10995 #define SDIO_ICR_TXUNDERRC_Pos (4U)
10996 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
10997 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
10998 #define SDIO_ICR_RXOVERRC_Pos (5U)
10999 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
11000 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
11001 #define SDIO_ICR_CMDRENDC_Pos (6U)
11002 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
11003 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
11004 #define SDIO_ICR_CMDSENTC_Pos (7U)
11005 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
11006 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
11007 #define SDIO_ICR_DATAENDC_Pos (8U)
11008 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
11009 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
11010 #define SDIO_ICR_STBITERRC_Pos (9U)
11011 #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
11012 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
11013 #define SDIO_ICR_DBCKENDC_Pos (10U)
11014 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
11015 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
11016 #define SDIO_ICR_SDIOITC_Pos (22U)
11017 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
11018 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
11019 #define SDIO_ICR_CEATAENDC_Pos (23U)
11020 #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
11021 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
11023 /****************** Bit definition for SDIO_MASK register *******************/
11024 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
11025 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
11026 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
11027 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
11028 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
11029 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
11030 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11031 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
11032 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
11033 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11034 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
11035 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
11036 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
11037 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
11038 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
11039 #define SDIO_MASK_RXOVERRIE_Pos (5U)
11040 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
11041 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
11042 #define SDIO_MASK_CMDRENDIE_Pos (6U)
11043 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
11044 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
11045 #define SDIO_MASK_CMDSENTIE_Pos (7U)
11046 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
11047 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
11048 #define SDIO_MASK_DATAENDIE_Pos (8U)
11049 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
11050 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
11051 #define SDIO_MASK_STBITERRIE_Pos (9U)
11052 #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
11053 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
11054 #define SDIO_MASK_DBCKENDIE_Pos (10U)
11055 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
11056 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
11057 #define SDIO_MASK_CMDACTIE_Pos (11U)
11058 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
11059 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
11060 #define SDIO_MASK_TXACTIE_Pos (12U)
11061 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
11062 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
11063 #define SDIO_MASK_RXACTIE_Pos (13U)
11064 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
11065 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
11066 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11067 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
11068 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
11069 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11070 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
11071 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
11072 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
11073 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
11074 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
11075 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
11076 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
11077 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
11078 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
11079 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
11080 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
11081 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
11082 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
11083 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
11084 #define SDIO_MASK_TXDAVLIE_Pos (20U)
11085 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
11086 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
11087 #define SDIO_MASK_RXDAVLIE_Pos (21U)
11088 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
11089 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
11090 #define SDIO_MASK_SDIOITIE_Pos (22U)
11091 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
11092 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
11093 #define SDIO_MASK_CEATAENDIE_Pos (23U)
11094 #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
11095 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
11097 /***************** Bit definition for SDIO_FIFOCNT register *****************/
11098 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11099 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
11100 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
11102 /****************** Bit definition for SDIO_FIFO register *******************/
11103 #define SDIO_FIFO_FIFODATA_Pos (0U)
11104 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
11105 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
11107 /******************************************************************************/
11108 /* */
11109 /* Serial Peripheral Interface */
11110 /* */
11111 /******************************************************************************/
11112 #define SPI_I2S_FULLDUPLEX_SUPPORT
11114 /******************* Bit definition for SPI_CR1 register ********************/
11115 #define SPI_CR1_CPHA_Pos (0U)
11116 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11117 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11118 #define SPI_CR1_CPOL_Pos (1U)
11119 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11120 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11121 #define SPI_CR1_MSTR_Pos (2U)
11122 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11123 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11125 #define SPI_CR1_BR_Pos (3U)
11126 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11127 #define SPI_CR1_BR SPI_CR1_BR_Msk
11128 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11129 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11130 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11132 #define SPI_CR1_SPE_Pos (6U)
11133 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11134 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
11135 #define SPI_CR1_LSBFIRST_Pos (7U)
11136 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11137 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11138 #define SPI_CR1_SSI_Pos (8U)
11139 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11140 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
11141 #define SPI_CR1_SSM_Pos (9U)
11142 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11143 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
11144 #define SPI_CR1_RXONLY_Pos (10U)
11145 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11146 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11147 #define SPI_CR1_DFF_Pos (11U)
11148 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
11149 #define SPI_CR1_DFF SPI_CR1_DFF_Msk
11150 #define SPI_CR1_CRCNEXT_Pos (12U)
11151 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11152 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11153 #define SPI_CR1_CRCEN_Pos (13U)
11154 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11155 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11156 #define SPI_CR1_BIDIOE_Pos (14U)
11157 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11158 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11159 #define SPI_CR1_BIDIMODE_Pos (15U)
11160 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11161 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11163 /******************* Bit definition for SPI_CR2 register ********************/
11164 #define SPI_CR2_RXDMAEN_Pos (0U)
11165 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11166 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11167 #define SPI_CR2_TXDMAEN_Pos (1U)
11168 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11169 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11170 #define SPI_CR2_SSOE_Pos (2U)
11171 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11172 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11173 #define SPI_CR2_FRF_Pos (4U)
11174 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11175 #define SPI_CR2_FRF SPI_CR2_FRF_Msk
11176 #define SPI_CR2_ERRIE_Pos (5U)
11177 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11178 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11179 #define SPI_CR2_RXNEIE_Pos (6U)
11180 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11181 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11182 #define SPI_CR2_TXEIE_Pos (7U)
11183 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11184 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11186 /******************** Bit definition for SPI_SR register ********************/
11187 #define SPI_SR_RXNE_Pos (0U)
11188 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11189 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
11190 #define SPI_SR_TXE_Pos (1U)
11191 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11192 #define SPI_SR_TXE SPI_SR_TXE_Msk
11193 #define SPI_SR_CHSIDE_Pos (2U)
11194 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11195 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11196 #define SPI_SR_UDR_Pos (3U)
11197 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11198 #define SPI_SR_UDR SPI_SR_UDR_Msk
11199 #define SPI_SR_CRCERR_Pos (4U)
11200 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11201 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11202 #define SPI_SR_MODF_Pos (5U)
11203 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11204 #define SPI_SR_MODF SPI_SR_MODF_Msk
11205 #define SPI_SR_OVR_Pos (6U)
11206 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11207 #define SPI_SR_OVR SPI_SR_OVR_Msk
11208 #define SPI_SR_BSY_Pos (7U)
11209 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11210 #define SPI_SR_BSY SPI_SR_BSY_Msk
11211 #define SPI_SR_FRE_Pos (8U)
11212 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11213 #define SPI_SR_FRE SPI_SR_FRE_Msk
11215 /******************** Bit definition for SPI_DR register ********************/
11216 #define SPI_DR_DR_Pos (0U)
11217 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11218 #define SPI_DR_DR SPI_DR_DR_Msk
11220 /******************* Bit definition for SPI_CRCPR register ******************/
11221 #define SPI_CRCPR_CRCPOLY_Pos (0U)
11222 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11223 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11225 /****************** Bit definition for SPI_RXCRCR register ******************/
11226 #define SPI_RXCRCR_RXCRC_Pos (0U)
11227 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11228 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11230 /****************** Bit definition for SPI_TXCRCR register ******************/
11231 #define SPI_TXCRCR_TXCRC_Pos (0U)
11232 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11233 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11235 /****************** Bit definition for SPI_I2SCFGR register *****************/
11236 #define SPI_I2SCFGR_CHLEN_Pos (0U)
11237 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11238 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11240 #define SPI_I2SCFGR_DATLEN_Pos (1U)
11241 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11242 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11243 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11244 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11246 #define SPI_I2SCFGR_CKPOL_Pos (3U)
11247 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11248 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11250 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
11251 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11252 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11253 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11254 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11256 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11257 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11258 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
11260 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
11261 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
11262 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
11263 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
11264 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
11266 #define SPI_I2SCFGR_I2SE_Pos (10U)
11267 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
11268 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
11269 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
11270 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
11271 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
11273 /****************** Bit definition for SPI_I2SPR register *******************/
11274 #define SPI_I2SPR_I2SDIV_Pos (0U)
11275 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
11276 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
11277 #define SPI_I2SPR_ODD_Pos (8U)
11278 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
11279 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
11280 #define SPI_I2SPR_MCKOE_Pos (9U)
11281 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
11282 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
11284 /******************************************************************************/
11285 /* */
11286 /* SYSCFG */
11287 /* */
11288 /******************************************************************************/
11289 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
11290 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11291 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11292 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
11293 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11294 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11295 /****************** Bit definition for SYSCFG_PMC register ******************/
11296 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
11297 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
11298 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
11299 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
11300 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
11301 
11302 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11303 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11304 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
11305 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
11306 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11307 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
11308 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
11309 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11310 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
11311 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
11312 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11313 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
11314 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
11318 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
11319 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
11320 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
11321 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
11322 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
11323 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
11324 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
11325 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
11326 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
11331 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
11332 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
11333 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
11334 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
11335 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
11336 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
11337 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
11338 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
11339 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
11344 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
11345 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
11346 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
11347 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
11348 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
11349 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
11350 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
11351 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
11352 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
11357 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
11358 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
11359 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
11360 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
11361 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
11362 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
11363 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
11364 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
11365 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
11367 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11368 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11369 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
11370 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
11371 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11372 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
11373 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
11374 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11375 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
11376 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
11377 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11378 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
11379 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
11384 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
11385 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
11386 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
11387 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
11388 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
11389 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
11390 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
11391 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
11392 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
11397 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
11398 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
11399 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
11400 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
11401 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
11402 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
11403 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
11404 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
11405 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
11410 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
11411 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
11412 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
11413 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
11414 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
11415 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
11416 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
11417 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
11418 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
11423 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
11424 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
11425 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
11426 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
11427 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
11428 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
11429 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
11430 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
11431 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
11433 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11434 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11435 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
11436 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
11437 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11438 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
11439 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
11440 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11441 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
11442 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
11443 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11444 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
11445 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
11450 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
11451 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
11452 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
11453 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
11454 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
11455 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
11456 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
11457 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
11458 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
11463 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
11464 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
11465 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
11466 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
11467 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
11468 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
11469 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
11470 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
11471 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
11476 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
11477 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
11478 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
11479 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
11480 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
11481 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
11482 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
11483 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
11484 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
11489 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
11490 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
11491 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
11492 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
11493 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
11494 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
11495 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
11496 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
11497 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
11499 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11500 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11501 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
11502 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
11503 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11504 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
11505 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
11506 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11507 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
11508 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
11509 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11510 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
11511 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
11516 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
11517 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
11518 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
11519 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
11520 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
11521 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
11522 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
11523 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
11528 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
11529 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
11530 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
11531 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
11532 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
11533 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
11534 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
11535 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
11540 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
11541 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
11542 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
11543 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
11544 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
11545 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
11546 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
11547 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
11552 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
11553 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
11554 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
11555 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
11556 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
11557 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
11558 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
11559 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
11561 /****************** Bit definition for SYSCFG_CMPCR register ****************/
11562 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11563 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
11564 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
11565 #define SYSCFG_CMPCR_READY_Pos (8U)
11566 #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
11567 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
11569 /******************************************************************************/
11570 /* */
11571 /* TIM */
11572 /* */
11573 /******************************************************************************/
11574 /******************* Bit definition for TIM_CR1 register ********************/
11575 #define TIM_CR1_CEN_Pos (0U)
11576 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
11577 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
11578 #define TIM_CR1_UDIS_Pos (1U)
11579 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
11580 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
11581 #define TIM_CR1_URS_Pos (2U)
11582 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
11583 #define TIM_CR1_URS TIM_CR1_URS_Msk
11584 #define TIM_CR1_OPM_Pos (3U)
11585 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
11586 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
11587 #define TIM_CR1_DIR_Pos (4U)
11588 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
11589 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
11591 #define TIM_CR1_CMS_Pos (5U)
11592 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
11593 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
11594 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
11595 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
11597 #define TIM_CR1_ARPE_Pos (7U)
11598 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
11599 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
11601 #define TIM_CR1_CKD_Pos (8U)
11602 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
11603 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
11604 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
11605 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
11607 /******************* Bit definition for TIM_CR2 register ********************/
11608 #define TIM_CR2_CCPC_Pos (0U)
11609 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
11610 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
11611 #define TIM_CR2_CCUS_Pos (2U)
11612 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
11613 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
11614 #define TIM_CR2_CCDS_Pos (3U)
11615 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
11616 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
11618 #define TIM_CR2_MMS_Pos (4U)
11619 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
11620 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
11621 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
11622 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
11623 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
11625 #define TIM_CR2_TI1S_Pos (7U)
11626 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
11627 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
11628 #define TIM_CR2_OIS1_Pos (8U)
11629 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
11630 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
11631 #define TIM_CR2_OIS1N_Pos (9U)
11632 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
11633 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
11634 #define TIM_CR2_OIS2_Pos (10U)
11635 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
11636 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
11637 #define TIM_CR2_OIS2N_Pos (11U)
11638 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
11639 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
11640 #define TIM_CR2_OIS3_Pos (12U)
11641 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
11642 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
11643 #define TIM_CR2_OIS3N_Pos (13U)
11644 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
11645 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
11646 #define TIM_CR2_OIS4_Pos (14U)
11647 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
11648 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
11650 /******************* Bit definition for TIM_SMCR register *******************/
11651 #define TIM_SMCR_SMS_Pos (0U)
11652 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
11653 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
11654 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
11655 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
11656 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
11658 #define TIM_SMCR_TS_Pos (4U)
11659 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
11660 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
11661 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
11662 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
11663 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
11665 #define TIM_SMCR_MSM_Pos (7U)
11666 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
11667 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
11669 #define TIM_SMCR_ETF_Pos (8U)
11670 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
11671 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
11672 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
11673 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
11674 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
11675 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
11677 #define TIM_SMCR_ETPS_Pos (12U)
11678 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
11679 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
11680 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
11681 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
11683 #define TIM_SMCR_ECE_Pos (14U)
11684 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
11685 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
11686 #define TIM_SMCR_ETP_Pos (15U)
11687 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
11688 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
11690 /******************* Bit definition for TIM_DIER register *******************/
11691 #define TIM_DIER_UIE_Pos (0U)
11692 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
11693 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
11694 #define TIM_DIER_CC1IE_Pos (1U)
11695 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
11696 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
11697 #define TIM_DIER_CC2IE_Pos (2U)
11698 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
11699 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
11700 #define TIM_DIER_CC3IE_Pos (3U)
11701 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
11702 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
11703 #define TIM_DIER_CC4IE_Pos (4U)
11704 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
11705 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
11706 #define TIM_DIER_COMIE_Pos (5U)
11707 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
11708 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
11709 #define TIM_DIER_TIE_Pos (6U)
11710 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
11711 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
11712 #define TIM_DIER_BIE_Pos (7U)
11713 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
11714 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
11715 #define TIM_DIER_UDE_Pos (8U)
11716 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
11717 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
11718 #define TIM_DIER_CC1DE_Pos (9U)
11719 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
11720 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
11721 #define TIM_DIER_CC2DE_Pos (10U)
11722 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
11723 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
11724 #define TIM_DIER_CC3DE_Pos (11U)
11725 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
11726 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
11727 #define TIM_DIER_CC4DE_Pos (12U)
11728 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
11729 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
11730 #define TIM_DIER_COMDE_Pos (13U)
11731 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
11732 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
11733 #define TIM_DIER_TDE_Pos (14U)
11734 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
11735 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
11737 /******************** Bit definition for TIM_SR register ********************/
11738 #define TIM_SR_UIF_Pos (0U)
11739 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
11740 #define TIM_SR_UIF TIM_SR_UIF_Msk
11741 #define TIM_SR_CC1IF_Pos (1U)
11742 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
11743 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
11744 #define TIM_SR_CC2IF_Pos (2U)
11745 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
11746 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
11747 #define TIM_SR_CC3IF_Pos (3U)
11748 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
11749 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
11750 #define TIM_SR_CC4IF_Pos (4U)
11751 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
11752 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
11753 #define TIM_SR_COMIF_Pos (5U)
11754 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
11755 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
11756 #define TIM_SR_TIF_Pos (6U)
11757 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
11758 #define TIM_SR_TIF TIM_SR_TIF_Msk
11759 #define TIM_SR_BIF_Pos (7U)
11760 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
11761 #define TIM_SR_BIF TIM_SR_BIF_Msk
11762 #define TIM_SR_CC1OF_Pos (9U)
11763 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
11764 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
11765 #define TIM_SR_CC2OF_Pos (10U)
11766 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
11767 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
11768 #define TIM_SR_CC3OF_Pos (11U)
11769 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
11770 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
11771 #define TIM_SR_CC4OF_Pos (12U)
11772 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
11773 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
11775 /******************* Bit definition for TIM_EGR register ********************/
11776 #define TIM_EGR_UG_Pos (0U)
11777 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
11778 #define TIM_EGR_UG TIM_EGR_UG_Msk
11779 #define TIM_EGR_CC1G_Pos (1U)
11780 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
11781 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
11782 #define TIM_EGR_CC2G_Pos (2U)
11783 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
11784 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
11785 #define TIM_EGR_CC3G_Pos (3U)
11786 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
11787 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
11788 #define TIM_EGR_CC4G_Pos (4U)
11789 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
11790 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
11791 #define TIM_EGR_COMG_Pos (5U)
11792 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
11793 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
11794 #define TIM_EGR_TG_Pos (6U)
11795 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
11796 #define TIM_EGR_TG TIM_EGR_TG_Msk
11797 #define TIM_EGR_BG_Pos (7U)
11798 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
11799 #define TIM_EGR_BG TIM_EGR_BG_Msk
11801 /****************** Bit definition for TIM_CCMR1 register *******************/
11802 #define TIM_CCMR1_CC1S_Pos (0U)
11803 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
11804 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
11805 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
11806 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
11808 #define TIM_CCMR1_OC1FE_Pos (2U)
11809 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
11810 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
11811 #define TIM_CCMR1_OC1PE_Pos (3U)
11812 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
11813 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
11815 #define TIM_CCMR1_OC1M_Pos (4U)
11816 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
11817 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
11818 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
11819 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
11820 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
11822 #define TIM_CCMR1_OC1CE_Pos (7U)
11823 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
11824 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
11826 #define TIM_CCMR1_CC2S_Pos (8U)
11827 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
11828 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
11829 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
11830 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
11832 #define TIM_CCMR1_OC2FE_Pos (10U)
11833 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
11834 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
11835 #define TIM_CCMR1_OC2PE_Pos (11U)
11836 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
11837 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
11839 #define TIM_CCMR1_OC2M_Pos (12U)
11840 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
11841 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
11842 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
11843 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
11844 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
11846 #define TIM_CCMR1_OC2CE_Pos (15U)
11847 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
11848 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
11850 /*----------------------------------------------------------------------------*/
11851 
11852 #define TIM_CCMR1_IC1PSC_Pos (2U)
11853 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
11854 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
11855 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
11856 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
11858 #define TIM_CCMR1_IC1F_Pos (4U)
11859 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
11860 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
11861 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
11862 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
11863 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
11864 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
11866 #define TIM_CCMR1_IC2PSC_Pos (10U)
11867 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
11868 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
11869 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
11870 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
11872 #define TIM_CCMR1_IC2F_Pos (12U)
11873 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
11874 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
11875 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
11876 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
11877 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
11878 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
11880 /****************** Bit definition for TIM_CCMR2 register *******************/
11881 #define TIM_CCMR2_CC3S_Pos (0U)
11882 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
11883 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
11884 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
11885 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
11887 #define TIM_CCMR2_OC3FE_Pos (2U)
11888 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
11889 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
11890 #define TIM_CCMR2_OC3PE_Pos (3U)
11891 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
11892 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
11894 #define TIM_CCMR2_OC3M_Pos (4U)
11895 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
11896 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
11897 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
11898 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
11899 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
11901 #define TIM_CCMR2_OC3CE_Pos (7U)
11902 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
11903 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
11905 #define TIM_CCMR2_CC4S_Pos (8U)
11906 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
11907 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
11908 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
11909 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
11911 #define TIM_CCMR2_OC4FE_Pos (10U)
11912 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
11913 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
11914 #define TIM_CCMR2_OC4PE_Pos (11U)
11915 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
11916 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
11918 #define TIM_CCMR2_OC4M_Pos (12U)
11919 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
11920 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
11921 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
11922 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
11923 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
11925 #define TIM_CCMR2_OC4CE_Pos (15U)
11926 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
11927 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
11929 /*----------------------------------------------------------------------------*/
11930 
11931 #define TIM_CCMR2_IC3PSC_Pos (2U)
11932 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
11933 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
11934 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
11935 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
11937 #define TIM_CCMR2_IC3F_Pos (4U)
11938 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
11939 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
11940 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
11941 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
11942 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
11943 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
11945 #define TIM_CCMR2_IC4PSC_Pos (10U)
11946 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
11947 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
11948 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
11949 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
11951 #define TIM_CCMR2_IC4F_Pos (12U)
11952 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
11953 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
11954 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
11955 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
11956 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
11957 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
11959 /******************* Bit definition for TIM_CCER register *******************/
11960 #define TIM_CCER_CC1E_Pos (0U)
11961 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
11962 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
11963 #define TIM_CCER_CC1P_Pos (1U)
11964 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
11965 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
11966 #define TIM_CCER_CC1NE_Pos (2U)
11967 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
11968 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
11969 #define TIM_CCER_CC1NP_Pos (3U)
11970 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
11971 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
11972 #define TIM_CCER_CC2E_Pos (4U)
11973 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
11974 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
11975 #define TIM_CCER_CC2P_Pos (5U)
11976 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
11977 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
11978 #define TIM_CCER_CC2NE_Pos (6U)
11979 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
11980 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
11981 #define TIM_CCER_CC2NP_Pos (7U)
11982 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
11983 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
11984 #define TIM_CCER_CC3E_Pos (8U)
11985 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
11986 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
11987 #define TIM_CCER_CC3P_Pos (9U)
11988 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
11989 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
11990 #define TIM_CCER_CC3NE_Pos (10U)
11991 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
11992 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
11993 #define TIM_CCER_CC3NP_Pos (11U)
11994 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
11995 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
11996 #define TIM_CCER_CC4E_Pos (12U)
11997 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
11998 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
11999 #define TIM_CCER_CC4P_Pos (13U)
12000 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12001 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12002 #define TIM_CCER_CC4NP_Pos (15U)
12003 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12004 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12006 /******************* Bit definition for TIM_CNT register ********************/
12007 #define TIM_CNT_CNT_Pos (0U)
12008 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12009 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
12011 /******************* Bit definition for TIM_PSC register ********************/
12012 #define TIM_PSC_PSC_Pos (0U)
12013 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12014 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
12016 /******************* Bit definition for TIM_ARR register ********************/
12017 #define TIM_ARR_ARR_Pos (0U)
12018 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12019 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
12021 /******************* Bit definition for TIM_RCR register ********************/
12022 #define TIM_RCR_REP_Pos (0U)
12023 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
12024 #define TIM_RCR_REP TIM_RCR_REP_Msk
12026 /******************* Bit definition for TIM_CCR1 register *******************/
12027 #define TIM_CCR1_CCR1_Pos (0U)
12028 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12029 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12031 /******************* Bit definition for TIM_CCR2 register *******************/
12032 #define TIM_CCR2_CCR2_Pos (0U)
12033 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12034 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12036 /******************* Bit definition for TIM_CCR3 register *******************/
12037 #define TIM_CCR3_CCR3_Pos (0U)
12038 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12039 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12041 /******************* Bit definition for TIM_CCR4 register *******************/
12042 #define TIM_CCR4_CCR4_Pos (0U)
12043 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12044 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12046 /******************* Bit definition for TIM_BDTR register *******************/
12047 #define TIM_BDTR_DTG_Pos (0U)
12048 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12049 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12050 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12051 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12052 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12053 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12054 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12055 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12056 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12057 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12059 #define TIM_BDTR_LOCK_Pos (8U)
12060 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12061 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12062 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12063 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12065 #define TIM_BDTR_OSSI_Pos (10U)
12066 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12067 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12068 #define TIM_BDTR_OSSR_Pos (11U)
12069 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12070 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12071 #define TIM_BDTR_BKE_Pos (12U)
12072 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12073 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12074 #define TIM_BDTR_BKP_Pos (13U)
12075 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12076 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12077 #define TIM_BDTR_AOE_Pos (14U)
12078 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12079 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12080 #define TIM_BDTR_MOE_Pos (15U)
12081 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12082 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12084 /******************* Bit definition for TIM_DCR register ********************/
12085 #define TIM_DCR_DBA_Pos (0U)
12086 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12087 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
12088 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12089 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12090 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12091 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12092 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12094 #define TIM_DCR_DBL_Pos (8U)
12095 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12096 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
12097 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12098 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12099 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12100 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12101 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12103 /******************* Bit definition for TIM_DMAR register *******************/
12104 #define TIM_DMAR_DMAB_Pos (0U)
12105 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12106 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12108 /******************* Bit definition for TIM_OR register *********************/
12109 #define TIM_OR_TI1_RMP_Pos (0U)
12110 #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
12111 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
12112 #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
12113 #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
12115 #define TIM_OR_TI4_RMP_Pos (6U)
12116 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
12117 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
12118 #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
12119 #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
12120 #define TIM_OR_ITR1_RMP_Pos (10U)
12121 #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
12122 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
12123 #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
12124 #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
12127 /******************************************************************************/
12128 /* */
12129 /* Universal Synchronous Asynchronous Receiver Transmitter */
12130 /* */
12131 /******************************************************************************/
12132 /******************* Bit definition for USART_SR register *******************/
12133 #define USART_SR_PE_Pos (0U)
12134 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
12135 #define USART_SR_PE USART_SR_PE_Msk
12136 #define USART_SR_FE_Pos (1U)
12137 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
12138 #define USART_SR_FE USART_SR_FE_Msk
12139 #define USART_SR_NE_Pos (2U)
12140 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
12141 #define USART_SR_NE USART_SR_NE_Msk
12142 #define USART_SR_ORE_Pos (3U)
12143 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
12144 #define USART_SR_ORE USART_SR_ORE_Msk
12145 #define USART_SR_IDLE_Pos (4U)
12146 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
12147 #define USART_SR_IDLE USART_SR_IDLE_Msk
12148 #define USART_SR_RXNE_Pos (5U)
12149 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
12150 #define USART_SR_RXNE USART_SR_RXNE_Msk
12151 #define USART_SR_TC_Pos (6U)
12152 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
12153 #define USART_SR_TC USART_SR_TC_Msk
12154 #define USART_SR_TXE_Pos (7U)
12155 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
12156 #define USART_SR_TXE USART_SR_TXE_Msk
12157 #define USART_SR_LBD_Pos (8U)
12158 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
12159 #define USART_SR_LBD USART_SR_LBD_Msk
12160 #define USART_SR_CTS_Pos (9U)
12161 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
12162 #define USART_SR_CTS USART_SR_CTS_Msk
12164 /******************* Bit definition for USART_DR register *******************/
12165 #define USART_DR_DR_Pos (0U)
12166 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
12167 #define USART_DR_DR USART_DR_DR_Msk
12169 /****************** Bit definition for USART_BRR register *******************/
12170 #define USART_BRR_DIV_Fraction_Pos (0U)
12171 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
12172 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
12173 #define USART_BRR_DIV_Mantissa_Pos (4U)
12174 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
12175 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
12177 /****************** Bit definition for USART_CR1 register *******************/
12178 #define USART_CR1_SBK_Pos (0U)
12179 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
12180 #define USART_CR1_SBK USART_CR1_SBK_Msk
12181 #define USART_CR1_RWU_Pos (1U)
12182 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
12183 #define USART_CR1_RWU USART_CR1_RWU_Msk
12184 #define USART_CR1_RE_Pos (2U)
12185 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
12186 #define USART_CR1_RE USART_CR1_RE_Msk
12187 #define USART_CR1_TE_Pos (3U)
12188 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
12189 #define USART_CR1_TE USART_CR1_TE_Msk
12190 #define USART_CR1_IDLEIE_Pos (4U)
12191 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
12192 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
12193 #define USART_CR1_RXNEIE_Pos (5U)
12194 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
12195 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
12196 #define USART_CR1_TCIE_Pos (6U)
12197 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
12198 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
12199 #define USART_CR1_TXEIE_Pos (7U)
12200 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
12201 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
12202 #define USART_CR1_PEIE_Pos (8U)
12203 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
12204 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
12205 #define USART_CR1_PS_Pos (9U)
12206 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
12207 #define USART_CR1_PS USART_CR1_PS_Msk
12208 #define USART_CR1_PCE_Pos (10U)
12209 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
12210 #define USART_CR1_PCE USART_CR1_PCE_Msk
12211 #define USART_CR1_WAKE_Pos (11U)
12212 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
12213 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
12214 #define USART_CR1_M_Pos (12U)
12215 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
12216 #define USART_CR1_M USART_CR1_M_Msk
12217 #define USART_CR1_UE_Pos (13U)
12218 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
12219 #define USART_CR1_UE USART_CR1_UE_Msk
12220 #define USART_CR1_OVER8_Pos (15U)
12221 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
12222 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
12224 /****************** Bit definition for USART_CR2 register *******************/
12225 #define USART_CR2_ADD_Pos (0U)
12226 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
12227 #define USART_CR2_ADD USART_CR2_ADD_Msk
12228 #define USART_CR2_LBDL_Pos (5U)
12229 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
12230 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
12231 #define USART_CR2_LBDIE_Pos (6U)
12232 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
12233 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
12234 #define USART_CR2_LBCL_Pos (8U)
12235 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
12236 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
12237 #define USART_CR2_CPHA_Pos (9U)
12238 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
12239 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
12240 #define USART_CR2_CPOL_Pos (10U)
12241 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
12242 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
12243 #define USART_CR2_CLKEN_Pos (11U)
12244 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
12245 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
12247 #define USART_CR2_STOP_Pos (12U)
12248 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
12249 #define USART_CR2_STOP USART_CR2_STOP_Msk
12250 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
12251 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
12253 #define USART_CR2_LINEN_Pos (14U)
12254 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
12255 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
12257 /****************** Bit definition for USART_CR3 register *******************/
12258 #define USART_CR3_EIE_Pos (0U)
12259 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
12260 #define USART_CR3_EIE USART_CR3_EIE_Msk
12261 #define USART_CR3_IREN_Pos (1U)
12262 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
12263 #define USART_CR3_IREN USART_CR3_IREN_Msk
12264 #define USART_CR3_IRLP_Pos (2U)
12265 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
12266 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
12267 #define USART_CR3_HDSEL_Pos (3U)
12268 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
12269 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
12270 #define USART_CR3_NACK_Pos (4U)
12271 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
12272 #define USART_CR3_NACK USART_CR3_NACK_Msk
12273 #define USART_CR3_SCEN_Pos (5U)
12274 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
12275 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
12276 #define USART_CR3_DMAR_Pos (6U)
12277 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
12278 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
12279 #define USART_CR3_DMAT_Pos (7U)
12280 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
12281 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
12282 #define USART_CR3_RTSE_Pos (8U)
12283 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
12284 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
12285 #define USART_CR3_CTSE_Pos (9U)
12286 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
12287 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
12288 #define USART_CR3_CTSIE_Pos (10U)
12289 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
12290 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
12291 #define USART_CR3_ONEBIT_Pos (11U)
12292 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
12293 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
12295 /****************** Bit definition for USART_GTPR register ******************/
12296 #define USART_GTPR_PSC_Pos (0U)
12297 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
12298 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
12299 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
12300 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
12301 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
12302 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
12303 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
12304 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
12305 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
12306 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
12308 #define USART_GTPR_GT_Pos (8U)
12309 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
12310 #define USART_GTPR_GT USART_GTPR_GT_Msk
12312 /******************************************************************************/
12313 /* */
12314 /* Window WATCHDOG */
12315 /* */
12316 /******************************************************************************/
12317 /******************* Bit definition for WWDG_CR register ********************/
12318 #define WWDG_CR_T_Pos (0U)
12319 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
12320 #define WWDG_CR_T WWDG_CR_T_Msk
12321 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
12322 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
12323 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
12324 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
12325 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
12326 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
12327 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
12328 /* Legacy defines */
12329 #define WWDG_CR_T0 WWDG_CR_T_0
12330 #define WWDG_CR_T1 WWDG_CR_T_1
12331 #define WWDG_CR_T2 WWDG_CR_T_2
12332 #define WWDG_CR_T3 WWDG_CR_T_3
12333 #define WWDG_CR_T4 WWDG_CR_T_4
12334 #define WWDG_CR_T5 WWDG_CR_T_5
12335 #define WWDG_CR_T6 WWDG_CR_T_6
12336 
12337 #define WWDG_CR_WDGA_Pos (7U)
12338 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
12339 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
12341 /******************* Bit definition for WWDG_CFR register *******************/
12342 #define WWDG_CFR_W_Pos (0U)
12343 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
12344 #define WWDG_CFR_W WWDG_CFR_W_Msk
12345 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
12346 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
12347 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
12348 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
12349 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
12350 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
12351 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
12352 /* Legacy defines */
12353 #define WWDG_CFR_W0 WWDG_CFR_W_0
12354 #define WWDG_CFR_W1 WWDG_CFR_W_1
12355 #define WWDG_CFR_W2 WWDG_CFR_W_2
12356 #define WWDG_CFR_W3 WWDG_CFR_W_3
12357 #define WWDG_CFR_W4 WWDG_CFR_W_4
12358 #define WWDG_CFR_W5 WWDG_CFR_W_5
12359 #define WWDG_CFR_W6 WWDG_CFR_W_6
12360 
12361 #define WWDG_CFR_WDGTB_Pos (7U)
12362 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
12363 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
12364 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
12365 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
12366 /* Legacy defines */
12367 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12368 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12369 
12370 #define WWDG_CFR_EWI_Pos (9U)
12371 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
12372 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
12374 /******************* Bit definition for WWDG_SR register ********************/
12375 #define WWDG_SR_EWIF_Pos (0U)
12376 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
12377 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
12380 /******************************************************************************/
12381 /* */
12382 /* DBG */
12383 /* */
12384 /******************************************************************************/
12385 /******************** Bit definition for DBGMCU_IDCODE register *************/
12386 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12387 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
12388 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12389 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
12390 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
12391 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12392 
12393 /******************** Bit definition for DBGMCU_CR register *****************/
12394 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12395 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
12396 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12397 #define DBGMCU_CR_DBG_STOP_Pos (1U)
12398 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
12399 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12400 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12401 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
12402 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12403 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12404 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
12405 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12406 
12407 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
12408 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
12409 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12410 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
12411 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
12413 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
12414 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12415 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
12416 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12417 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12418 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
12419 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12420 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12421 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
12422 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12423 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12424 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
12425 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12426 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12427 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
12428 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12429 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12430 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
12431 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12432 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12433 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
12434 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12435 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12436 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
12437 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12438 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12439 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
12440 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12441 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12442 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
12443 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12444 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12445 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
12446 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12447 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12448 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
12449 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12450 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12451 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
12452 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12453 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12454 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
12455 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12456 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12457 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
12458 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12459 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12460 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
12461 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12462 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12463 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
12464 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12465 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
12466 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
12467 
12468 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
12469 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12470 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
12471 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12472 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12473 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
12474 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12475 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12476 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
12477 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12478 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12479 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
12480 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12481 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12482 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
12483 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12484 
12485 /******************************************************************************/
12486 /* */
12487 /* USB_OTG */
12488 /* */
12489 /******************************************************************************/
12490 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
12491 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
12492 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
12493 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
12494 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
12495 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
12496 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
12497 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
12498 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
12499 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
12500 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
12501 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
12502 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
12503 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
12504 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
12505 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
12506 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
12507 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
12508 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
12509 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
12510 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
12511 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
12512 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
12513 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
12514 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
12515 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
12516 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
12517 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
12518 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
12519 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
12520 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
12522 /******************** Bit definition forUSB_OTG_HCFG register ********************/
12523 
12524 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
12525 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
12526 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
12527 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
12528 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
12529 #define USB_OTG_HCFG_FSLSS_Pos (2U)
12530 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
12531 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
12533 /******************** Bit definition for USB_OTG_DCFG register ********************/
12534 
12535 #define USB_OTG_DCFG_DSPD_Pos (0U)
12536 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
12537 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
12538 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
12539 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
12540 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
12541 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
12542 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
12544 #define USB_OTG_DCFG_DAD_Pos (4U)
12545 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
12546 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
12547 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
12548 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
12549 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
12550 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
12551 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
12552 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
12553 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
12555 #define USB_OTG_DCFG_PFIVL_Pos (11U)
12556 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
12557 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
12558 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
12559 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
12561 #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
12562 #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
12563 #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
12565 #define USB_OTG_DCFG_ERRATIM_Pos (15U)
12566 #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
12567 #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
12569 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
12570 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
12571 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
12572 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
12573 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
12575 /******************** Bit definition for USB_OTG_PCGCR register ********************/
12576 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
12577 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
12578 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
12579 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
12580 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
12581 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
12582 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
12583 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
12584 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
12586 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
12587 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
12588 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
12589 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
12590 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
12591 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
12592 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
12593 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
12594 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
12595 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
12596 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
12597 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
12598 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
12599 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
12600 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
12601 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
12602 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
12603 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
12604 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
12606 /******************** Bit definition for USB_OTG_DCTL register ********************/
12607 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
12608 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
12609 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
12610 #define USB_OTG_DCTL_SDIS_Pos (1U)
12611 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
12612 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
12613 #define USB_OTG_DCTL_GINSTS_Pos (2U)
12614 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
12615 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
12616 #define USB_OTG_DCTL_GONSTS_Pos (3U)
12617 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
12618 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
12620 #define USB_OTG_DCTL_TCTL_Pos (4U)
12621 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
12622 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
12623 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
12624 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
12625 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
12626 #define USB_OTG_DCTL_SGINAK_Pos (7U)
12627 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
12628 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
12629 #define USB_OTG_DCTL_CGINAK_Pos (8U)
12630 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
12631 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
12632 #define USB_OTG_DCTL_SGONAK_Pos (9U)
12633 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
12634 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
12635 #define USB_OTG_DCTL_CGONAK_Pos (10U)
12636 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
12637 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
12638 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
12639 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
12640 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
12642 /******************** Bit definition for USB_OTG_HFIR register ********************/
12643 #define USB_OTG_HFIR_FRIVL_Pos (0U)
12644 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
12645 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
12647 /******************** Bit definition for USB_OTG_HFNUM register ********************/
12648 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
12649 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
12650 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
12651 #define USB_OTG_HFNUM_FTREM_Pos (16U)
12652 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
12653 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
12655 /******************** Bit definition for USB_OTG_DSTS register ********************/
12656 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
12657 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
12658 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
12660 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
12661 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
12662 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
12663 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
12664 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
12665 #define USB_OTG_DSTS_EERR_Pos (3U)
12666 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
12667 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
12668 #define USB_OTG_DSTS_FNSOF_Pos (8U)
12669 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
12670 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
12672 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
12673 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
12674 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
12675 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
12676 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
12677 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12678 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
12679 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12680 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12681 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12682 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12683 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12684 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
12685 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
12686 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
12687 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
12688 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
12689 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
12690 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
12691 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
12692 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
12694 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
12695 
12696 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
12697 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12698 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
12699 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12700 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12701 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12702 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
12703 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
12704 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
12705 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
12706 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
12707 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
12708 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
12709 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
12710 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
12711 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
12712 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
12713 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
12714 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
12715 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
12716 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
12717 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
12718 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
12719 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
12720 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
12721 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
12722 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
12723 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
12724 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
12725 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
12726 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
12727 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
12728 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
12729 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
12730 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
12731 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
12732 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
12733 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
12734 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
12735 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
12736 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
12737 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
12738 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
12739 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
12740 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
12741 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
12742 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
12743 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
12744 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
12745 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
12746 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
12747 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
12748 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
12749 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
12750 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
12751 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
12752 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
12753 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
12754 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
12755 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
12756 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
12758 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
12759 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
12760 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
12761 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
12762 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
12763 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
12764 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
12765 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
12766 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
12767 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
12768 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
12769 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
12770 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
12771 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
12772 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
12773 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
12776 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
12777 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12778 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
12779 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12780 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12781 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12782 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12783 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12784 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
12785 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
12786 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
12787 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
12788 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
12789 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
12791 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
12792 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
12793 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
12794 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
12795 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
12796 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
12797 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
12798 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
12799 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
12800 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
12801 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
12802 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
12803 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
12804 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
12805 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
12806 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
12807 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
12808 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
12809 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
12810 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
12811 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
12812 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
12813 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
12814 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
12815 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
12817 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
12818 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
12819 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
12820 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
12821 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
12822 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12823 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
12824 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12825 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12826 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12827 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12828 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12829 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12830 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12831 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12833 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
12834 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12835 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
12836 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12837 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12838 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12839 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12840 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12841 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12842 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12843 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12845 /******************** Bit definition for USB_OTG_HAINT register ********************/
12846 #define USB_OTG_HAINT_HAINT_Pos (0U)
12847 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
12848 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
12850 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
12851 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
12852 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
12853 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
12854 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
12855 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
12856 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
12857 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
12858 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
12859 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
12860 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
12861 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
12862 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
12863 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
12864 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
12865 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
12866 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
12867 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
12868 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
12869 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
12870 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
12871 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
12872 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
12873 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
12874 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
12875 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
12876 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
12877 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
12878 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
12879 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
12880 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
12881 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
12882 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
12883 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
12884 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
12885 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
12886 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
12887 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
12888 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
12889 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
12890 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
12891 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
12892 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
12893 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
12894 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
12895 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
12896 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
12897 #define USB_OTG_GINTSTS_SOF_Pos (3U)
12898 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
12899 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
12900 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
12901 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
12902 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
12903 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
12904 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
12905 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
12906 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
12907 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
12908 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
12909 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
12910 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
12911 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
12912 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
12913 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
12914 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
12915 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
12916 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
12917 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
12918 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
12919 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
12920 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
12921 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
12922 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
12923 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
12924 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
12925 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
12926 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
12927 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
12928 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
12929 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
12930 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
12931 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
12932 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
12933 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
12934 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
12935 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
12936 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
12937 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
12938 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
12939 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
12940 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
12941 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
12942 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
12943 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
12944 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
12945 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
12946 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
12947 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
12948 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
12949 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
12950 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
12951 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
12952 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
12953 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
12954 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
12955 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
12956 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
12957 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
12958 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
12959 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
12960 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
12961 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
12962 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
12963 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
12964 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
12965 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
12967 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
12968 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
12969 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
12970 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
12971 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
12972 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
12973 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
12974 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
12975 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
12976 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
12977 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
12978 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
12979 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
12980 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
12981 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
12982 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
12983 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
12984 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
12985 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
12986 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
12987 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
12988 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
12989 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
12990 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
12991 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
12992 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
12993 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
12994 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
12995 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
12996 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
12997 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
12998 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
12999 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
13000 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
13001 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
13002 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
13003 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
13004 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
13005 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
13006 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
13007 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
13008 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
13009 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
13010 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
13011 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
13012 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
13013 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
13014 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
13015 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
13016 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
13017 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
13018 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
13019 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
13020 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
13021 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
13022 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
13023 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
13024 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
13025 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
13026 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
13027 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
13028 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
13029 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
13030 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
13031 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
13032 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
13033 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
13034 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
13035 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
13036 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
13037 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
13038 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
13039 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
13040 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
13041 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
13042 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
13043 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
13044 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
13045 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
13047 /******************** Bit definition for USB_OTG_DAINT register ********************/
13048 #define USB_OTG_DAINT_IEPINT_Pos (0U)
13049 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
13050 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
13051 #define USB_OTG_DAINT_OEPINT_Pos (16U)
13052 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
13053 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
13055 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
13056 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
13057 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
13058 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
13060 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
13061 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
13062 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
13063 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
13064 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
13065 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
13066 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
13067 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
13068 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
13069 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
13070 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
13071 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
13072 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
13074 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
13075 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
13076 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
13077 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
13078 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
13079 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
13080 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
13082 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
13083 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
13084 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
13085 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
13087 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
13088 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
13089 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
13090 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
13092 /******************** Bit definition for OTG register ********************/
13093 #define USB_OTG_NPTXFSA_Pos (0U)
13094 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
13095 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
13096 #define USB_OTG_NPTXFD_Pos (16U)
13097 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
13098 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
13099 #define USB_OTG_TX0FSA_Pos (0U)
13100 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
13101 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
13102 #define USB_OTG_TX0FD_Pos (16U)
13103 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
13104 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
13106 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
13107 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
13108 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
13109 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
13111 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
13112 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
13113 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
13114 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
13116 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
13117 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13118 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
13119 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13120 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13121 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13122 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13123 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13124 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13125 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13126 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13128 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
13129 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13130 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
13131 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13132 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13133 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13134 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13135 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13136 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13137 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13139 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
13140 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
13141 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
13142 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
13143 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
13144 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
13145 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
13147 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
13148 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13149 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
13150 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13151 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13152 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13153 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13154 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13155 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13156 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13157 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13158 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13159 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
13160 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
13161 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
13163 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
13164 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13165 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
13166 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13167 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13168 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13169 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13170 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13171 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13172 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13173 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13174 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13175 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
13176 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
13177 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
13179 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
13180 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
13181 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
13182 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
13184 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
13185 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
13186 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
13187 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
13188 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
13189 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
13190 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
13192 /******************** Bit definition for USB_OTG_GCCFG register ********************/
13193 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
13194 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
13195 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
13196 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
13197 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
13198 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
13199 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
13200 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
13201 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
13202 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
13203 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
13204 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
13205 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
13206 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
13207 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
13208 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
13209 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
13210 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
13212 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
13213 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
13214 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
13215 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
13216 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
13217 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
13218 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
13220 /******************** Bit definition for USB_OTG_CID register ********************/
13221 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
13222 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
13223 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
13225 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
13226 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
13227 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
13228 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
13229 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
13230 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
13231 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
13232 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
13233 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
13234 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
13235 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
13236 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
13237 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
13238 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
13239 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
13240 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
13241 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
13242 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
13243 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
13244 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
13245 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
13246 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
13247 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
13248 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
13249 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
13250 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
13251 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
13252 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
13254 /******************** Bit definition for USB_OTG_HPRT register ********************/
13255 #define USB_OTG_HPRT_PCSTS_Pos (0U)
13256 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
13257 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
13258 #define USB_OTG_HPRT_PCDET_Pos (1U)
13259 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
13260 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
13261 #define USB_OTG_HPRT_PENA_Pos (2U)
13262 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
13263 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
13264 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
13265 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
13266 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
13267 #define USB_OTG_HPRT_POCA_Pos (4U)
13268 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
13269 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
13270 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
13271 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
13272 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
13273 #define USB_OTG_HPRT_PRES_Pos (6U)
13274 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
13275 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
13276 #define USB_OTG_HPRT_PSUSP_Pos (7U)
13277 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
13278 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
13279 #define USB_OTG_HPRT_PRST_Pos (8U)
13280 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
13281 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
13283 #define USB_OTG_HPRT_PLSTS_Pos (10U)
13284 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
13285 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
13286 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
13287 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
13288 #define USB_OTG_HPRT_PPWR_Pos (12U)
13289 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
13290 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
13292 #define USB_OTG_HPRT_PTCTL_Pos (13U)
13293 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
13294 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
13295 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
13296 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
13297 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
13298 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
13300 #define USB_OTG_HPRT_PSPD_Pos (17U)
13301 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
13302 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
13303 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
13304 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
13306 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
13307 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
13308 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
13309 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
13310 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
13311 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
13312 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
13313 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
13314 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
13315 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
13316 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
13317 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
13318 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
13319 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
13320 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
13321 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
13322 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
13323 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
13324 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
13325 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
13326 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
13327 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
13328 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
13329 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
13330 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
13331 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
13332 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
13333 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
13334 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
13335 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
13336 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
13337 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
13338 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
13339 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
13341 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
13342 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
13343 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
13344 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
13345 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
13346 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
13347 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
13349 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
13350 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
13351 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
13352 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
13353 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
13354 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
13355 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
13356 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
13357 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
13358 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
13359 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
13360 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
13361 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
13363 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
13364 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
13365 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
13366 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
13367 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
13368 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
13369 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
13370 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
13372 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
13373 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13374 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
13375 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13376 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13377 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13378 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13379 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
13380 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
13381 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
13382 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
13383 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
13384 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
13385 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
13386 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
13387 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
13388 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
13389 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
13390 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
13391 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
13392 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
13393 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
13394 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
13395 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
13396 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
13398 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
13399 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
13400 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
13401 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
13403 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
13404 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
13405 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
13406 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
13407 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
13408 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
13409 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
13410 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
13411 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
13412 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
13413 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
13414 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
13415 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
13417 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
13418 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
13419 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
13420 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
13421 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
13423 #define USB_OTG_HCCHAR_MC_Pos (20U)
13424 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
13425 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
13426 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
13427 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
13429 #define USB_OTG_HCCHAR_DAD_Pos (22U)
13430 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
13431 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
13432 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
13433 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
13434 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
13435 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
13436 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
13437 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
13438 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
13439 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
13440 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
13441 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
13442 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
13443 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
13444 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
13445 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
13446 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
13447 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
13449 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
13450 
13451 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
13452 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
13453 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
13454 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13455 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13456 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13457 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13458 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13459 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13460 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13462 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
13463 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
13464 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
13465 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13466 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13467 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13468 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13469 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13470 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13471 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13473 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
13474 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
13475 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
13476 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
13477 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
13478 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
13479 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
13480 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
13481 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
13482 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
13483 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
13485 /******************** Bit definition for USB_OTG_HCINT register ********************/
13486 #define USB_OTG_HCINT_XFRC_Pos (0U)
13487 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
13488 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
13489 #define USB_OTG_HCINT_CHH_Pos (1U)
13490 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
13491 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
13492 #define USB_OTG_HCINT_AHBERR_Pos (2U)
13493 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
13494 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
13495 #define USB_OTG_HCINT_STALL_Pos (3U)
13496 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
13497 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
13498 #define USB_OTG_HCINT_NAK_Pos (4U)
13499 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
13500 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
13501 #define USB_OTG_HCINT_ACK_Pos (5U)
13502 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
13503 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
13504 #define USB_OTG_HCINT_NYET_Pos (6U)
13505 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
13506 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
13507 #define USB_OTG_HCINT_TXERR_Pos (7U)
13508 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
13509 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
13510 #define USB_OTG_HCINT_BBERR_Pos (8U)
13511 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
13512 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
13513 #define USB_OTG_HCINT_FRMOR_Pos (9U)
13514 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
13515 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
13516 #define USB_OTG_HCINT_DTERR_Pos (10U)
13517 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
13518 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
13520 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
13521 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
13522 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
13523 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
13524 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
13525 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
13526 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
13527 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
13528 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
13529 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
13530 #define USB_OTG_DIEPINT_TOC_Pos (3U)
13531 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
13532 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
13533 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
13534 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
13535 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
13536 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
13537 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
13538 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
13539 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
13540 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
13541 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
13542 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
13543 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
13544 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
13545 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
13546 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
13547 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
13548 #define USB_OTG_DIEPINT_BNA_Pos (9U)
13549 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
13550 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
13551 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
13552 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
13553 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
13554 #define USB_OTG_DIEPINT_BERR_Pos (12U)
13555 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
13556 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
13557 #define USB_OTG_DIEPINT_NAK_Pos (13U)
13558 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
13559 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
13561 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
13562 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
13563 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
13564 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
13565 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
13566 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
13567 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
13568 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
13569 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
13570 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
13571 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
13572 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
13573 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
13574 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
13575 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
13576 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
13577 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
13578 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
13579 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
13580 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
13581 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
13582 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
13583 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
13584 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
13585 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
13586 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
13587 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
13588 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
13589 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
13590 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
13591 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
13592 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
13593 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
13594 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
13596 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
13597 
13598 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
13599 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
13600 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
13601 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
13602 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
13603 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
13604 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
13605 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
13606 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
13607 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
13608 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
13609 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
13610 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
13611 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
13612 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
13613 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
13614 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
13615 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
13616 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
13617 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
13618 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
13619 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
13620 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
13621 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
13623 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
13624 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
13625 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
13626 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
13628 /******************** Bit definition for USB_OTG_HCDMA register ********************/
13629 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
13630 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
13631 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
13633 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
13634 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
13635 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
13636 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
13638 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
13639 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
13640 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
13641 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
13642 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
13643 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
13644 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
13646 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
13647 
13648 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
13649 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
13650 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
13651 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
13652 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
13653 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
13654 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
13655 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
13656 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
13657 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
13658 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
13659 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
13660 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
13661 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
13662 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
13663 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
13664 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
13665 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
13666 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
13667 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
13668 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
13669 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
13670 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
13671 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
13672 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
13673 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
13674 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
13675 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
13676 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
13677 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
13678 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
13679 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
13680 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
13681 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
13682 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
13683 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
13684 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
13685 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
13687 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
13688 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
13689 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
13690 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
13691 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
13692 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
13693 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
13694 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
13695 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
13696 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
13697 #define USB_OTG_DOEPINT_STUP_Pos (3U)
13698 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
13699 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
13700 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
13701 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
13702 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
13703 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
13704 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
13705 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
13706 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
13707 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
13708 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
13709 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
13710 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
13711 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
13712 #define USB_OTG_DOEPINT_NAK_Pos (13U)
13713 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
13714 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
13715 #define USB_OTG_DOEPINT_NYET_Pos (14U)
13716 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
13717 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
13718 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
13719 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
13720 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
13721 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
13722 
13723 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
13724 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
13725 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
13726 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
13727 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
13728 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
13730 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
13731 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
13732 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
13733 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
13734 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
13736 /******************** Bit definition for PCGCCTL register ********************/
13737 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
13738 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
13739 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
13740 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
13741 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
13742 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
13743 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
13744 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
13745 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
13747 /* Legacy define */
13748 /******************** Bit definition for OTG register ********************/
13749 #define USB_OTG_CHNUM_Pos (0U)
13750 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
13751 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
13752 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
13753 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
13754 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
13755 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
13756 #define USB_OTG_BCNT_Pos (4U)
13757 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
13758 #define USB_OTG_BCNT USB_OTG_BCNT_Msk
13760 #define USB_OTG_DPID_Pos (15U)
13761 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
13762 #define USB_OTG_DPID USB_OTG_DPID_Msk
13763 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
13764 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
13766 #define USB_OTG_PKTSTS_Pos (17U)
13767 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
13768 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
13769 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
13770 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
13771 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
13772 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
13774 #define USB_OTG_EPNUM_Pos (0U)
13775 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
13776 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
13777 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
13778 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
13779 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
13780 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
13782 #define USB_OTG_FRMNUM_Pos (21U)
13783 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
13784 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
13785 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
13786 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
13787 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
13788 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
13801 /******************************* ADC Instances ********************************/
13802 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
13803  ((INSTANCE) == ADC2) || \
13804  ((INSTANCE) == ADC3))
13805 
13806 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
13807 
13808 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
13809 
13810 /******************************* CAN Instances ********************************/
13811 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
13812  ((INSTANCE) == CAN2))
13813 /******************************* CRC Instances ********************************/
13814 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
13815 
13816 /******************************* DAC Instances ********************************/
13817 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
13818 
13819 
13820 /******************************** DMA Instances *******************************/
13821 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
13822  ((INSTANCE) == DMA1_Stream1) || \
13823  ((INSTANCE) == DMA1_Stream2) || \
13824  ((INSTANCE) == DMA1_Stream3) || \
13825  ((INSTANCE) == DMA1_Stream4) || \
13826  ((INSTANCE) == DMA1_Stream5) || \
13827  ((INSTANCE) == DMA1_Stream6) || \
13828  ((INSTANCE) == DMA1_Stream7) || \
13829  ((INSTANCE) == DMA2_Stream0) || \
13830  ((INSTANCE) == DMA2_Stream1) || \
13831  ((INSTANCE) == DMA2_Stream2) || \
13832  ((INSTANCE) == DMA2_Stream3) || \
13833  ((INSTANCE) == DMA2_Stream4) || \
13834  ((INSTANCE) == DMA2_Stream5) || \
13835  ((INSTANCE) == DMA2_Stream6) || \
13836  ((INSTANCE) == DMA2_Stream7))
13837 
13838 /******************************* GPIO Instances *******************************/
13839 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
13840  ((INSTANCE) == GPIOB) || \
13841  ((INSTANCE) == GPIOC) || \
13842  ((INSTANCE) == GPIOD) || \
13843  ((INSTANCE) == GPIOE) || \
13844  ((INSTANCE) == GPIOF) || \
13845  ((INSTANCE) == GPIOG) || \
13846  ((INSTANCE) == GPIOH) || \
13847  ((INSTANCE) == GPIOI))
13848 
13849 /******************************** I2C Instances *******************************/
13850 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
13851  ((INSTANCE) == I2C2) || \
13852  ((INSTANCE) == I2C3))
13853 
13854 /******************************* SMBUS Instances ******************************/
13855 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
13856 
13857 /******************************** I2S Instances *******************************/
13858 
13859 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
13860  ((INSTANCE) == SPI3))
13861 
13862 /*************************** I2S Extended Instances ***************************/
13863 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
13864  ((INSTANCE) == I2S3ext))
13865 /* Legacy Defines */
13866 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
13867 
13868 /******************************* RNG Instances ********************************/
13869 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
13870 
13871 /****************************** RTC Instances *********************************/
13872 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
13873 
13874 
13875 /******************************** SPI Instances *******************************/
13876 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
13877  ((INSTANCE) == SPI2) || \
13878  ((INSTANCE) == SPI3))
13879 
13880 
13881 /****************** TIM Instances : All supported instances *******************/
13882 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13883  ((INSTANCE) == TIM2) || \
13884  ((INSTANCE) == TIM3) || \
13885  ((INSTANCE) == TIM4) || \
13886  ((INSTANCE) == TIM5) || \
13887  ((INSTANCE) == TIM6) || \
13888  ((INSTANCE) == TIM7) || \
13889  ((INSTANCE) == TIM8) || \
13890  ((INSTANCE) == TIM9) || \
13891  ((INSTANCE) == TIM10)|| \
13892  ((INSTANCE) == TIM11)|| \
13893  ((INSTANCE) == TIM12)|| \
13894  ((INSTANCE) == TIM13)|| \
13895  ((INSTANCE) == TIM14))
13896 
13897 /************* TIM Instances : at least 1 capture/compare channel *************/
13898 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13899  ((INSTANCE) == TIM2) || \
13900  ((INSTANCE) == TIM3) || \
13901  ((INSTANCE) == TIM4) || \
13902  ((INSTANCE) == TIM5) || \
13903  ((INSTANCE) == TIM8) || \
13904  ((INSTANCE) == TIM9) || \
13905  ((INSTANCE) == TIM10) || \
13906  ((INSTANCE) == TIM11) || \
13907  ((INSTANCE) == TIM12) || \
13908  ((INSTANCE) == TIM13) || \
13909  ((INSTANCE) == TIM14))
13910 
13911 /************ TIM Instances : at least 2 capture/compare channels *************/
13912 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13913  ((INSTANCE) == TIM2) || \
13914  ((INSTANCE) == TIM3) || \
13915  ((INSTANCE) == TIM4) || \
13916  ((INSTANCE) == TIM5) || \
13917  ((INSTANCE) == TIM8) || \
13918  ((INSTANCE) == TIM9) || \
13919  ((INSTANCE) == TIM12))
13920 
13921 /************ TIM Instances : at least 3 capture/compare channels *************/
13922 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13923  ((INSTANCE) == TIM2) || \
13924  ((INSTANCE) == TIM3) || \
13925  ((INSTANCE) == TIM4) || \
13926  ((INSTANCE) == TIM5) || \
13927  ((INSTANCE) == TIM8))
13928 
13929 /************ TIM Instances : at least 4 capture/compare channels *************/
13930 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13931  ((INSTANCE) == TIM2) || \
13932  ((INSTANCE) == TIM3) || \
13933  ((INSTANCE) == TIM4) || \
13934  ((INSTANCE) == TIM5) || \
13935  ((INSTANCE) == TIM8))
13936 
13937 /******************** TIM Instances : Advanced-control timers *****************/
13938 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13939  ((INSTANCE) == TIM8))
13940 
13941 /******************* TIM Instances : Timer input XOR function *****************/
13942 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13943  ((INSTANCE) == TIM2) || \
13944  ((INSTANCE) == TIM3) || \
13945  ((INSTANCE) == TIM4) || \
13946  ((INSTANCE) == TIM5) || \
13947  ((INSTANCE) == TIM8))
13948 
13949 /****************** TIM Instances : DMA requests generation (UDE) *************/
13950 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13951  ((INSTANCE) == TIM2) || \
13952  ((INSTANCE) == TIM3) || \
13953  ((INSTANCE) == TIM4) || \
13954  ((INSTANCE) == TIM5) || \
13955  ((INSTANCE) == TIM6) || \
13956  ((INSTANCE) == TIM7) || \
13957  ((INSTANCE) == TIM8))
13958 
13959 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
13960 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13961  ((INSTANCE) == TIM2) || \
13962  ((INSTANCE) == TIM3) || \
13963  ((INSTANCE) == TIM4) || \
13964  ((INSTANCE) == TIM5) || \
13965  ((INSTANCE) == TIM8))
13966 
13967 /************ TIM Instances : DMA requests generation (COMDE) *****************/
13968 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13969  ((INSTANCE) == TIM2) || \
13970  ((INSTANCE) == TIM3) || \
13971  ((INSTANCE) == TIM4) || \
13972  ((INSTANCE) == TIM5) || \
13973  ((INSTANCE) == TIM8))
13974 
13975 /******************** TIM Instances : DMA burst feature ***********************/
13976 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13977  ((INSTANCE) == TIM2) || \
13978  ((INSTANCE) == TIM3) || \
13979  ((INSTANCE) == TIM4) || \
13980  ((INSTANCE) == TIM5) || \
13981  ((INSTANCE) == TIM8))
13982 
13983 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
13984 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13985  ((INSTANCE) == TIM2) || \
13986  ((INSTANCE) == TIM3) || \
13987  ((INSTANCE) == TIM4) || \
13988  ((INSTANCE) == TIM5) || \
13989  ((INSTANCE) == TIM6) || \
13990  ((INSTANCE) == TIM7) || \
13991  ((INSTANCE) == TIM8))
13992 
13993 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
13994 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13995  ((INSTANCE) == TIM2) || \
13996  ((INSTANCE) == TIM3) || \
13997  ((INSTANCE) == TIM4) || \
13998  ((INSTANCE) == TIM5) || \
13999  ((INSTANCE) == TIM8) || \
14000  ((INSTANCE) == TIM9) || \
14001  ((INSTANCE) == TIM12))
14002 /********************** TIM Instances : 32 bit Counter ************************/
14003 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
14004  ((INSTANCE) == TIM5))
14005 
14006 /***************** TIM Instances : external trigger input available ************/
14007 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14008  ((INSTANCE) == TIM2) || \
14009  ((INSTANCE) == TIM3) || \
14010  ((INSTANCE) == TIM4) || \
14011  ((INSTANCE) == TIM5) || \
14012  ((INSTANCE) == TIM8))
14013 
14014 /****************** TIM Instances : remapping capability **********************/
14015 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
14016  ((INSTANCE) == TIM5) || \
14017  ((INSTANCE) == TIM11))
14018 
14019 /******************* TIM Instances : output(s) available **********************/
14020 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14021  ((((INSTANCE) == TIM1) && \
14022  (((CHANNEL) == TIM_CHANNEL_1) || \
14023  ((CHANNEL) == TIM_CHANNEL_2) || \
14024  ((CHANNEL) == TIM_CHANNEL_3) || \
14025  ((CHANNEL) == TIM_CHANNEL_4))) \
14026  || \
14027  (((INSTANCE) == TIM2) && \
14028  (((CHANNEL) == TIM_CHANNEL_1) || \
14029  ((CHANNEL) == TIM_CHANNEL_2) || \
14030  ((CHANNEL) == TIM_CHANNEL_3) || \
14031  ((CHANNEL) == TIM_CHANNEL_4))) \
14032  || \
14033  (((INSTANCE) == TIM3) && \
14034  (((CHANNEL) == TIM_CHANNEL_1) || \
14035  ((CHANNEL) == TIM_CHANNEL_2) || \
14036  ((CHANNEL) == TIM_CHANNEL_3) || \
14037  ((CHANNEL) == TIM_CHANNEL_4))) \
14038  || \
14039  (((INSTANCE) == TIM4) && \
14040  (((CHANNEL) == TIM_CHANNEL_1) || \
14041  ((CHANNEL) == TIM_CHANNEL_2) || \
14042  ((CHANNEL) == TIM_CHANNEL_3) || \
14043  ((CHANNEL) == TIM_CHANNEL_4))) \
14044  || \
14045  (((INSTANCE) == TIM5) && \
14046  (((CHANNEL) == TIM_CHANNEL_1) || \
14047  ((CHANNEL) == TIM_CHANNEL_2) || \
14048  ((CHANNEL) == TIM_CHANNEL_3) || \
14049  ((CHANNEL) == TIM_CHANNEL_4))) \
14050  || \
14051  (((INSTANCE) == TIM8) && \
14052  (((CHANNEL) == TIM_CHANNEL_1) || \
14053  ((CHANNEL) == TIM_CHANNEL_2) || \
14054  ((CHANNEL) == TIM_CHANNEL_3) || \
14055  ((CHANNEL) == TIM_CHANNEL_4))) \
14056  || \
14057  (((INSTANCE) == TIM9) && \
14058  (((CHANNEL) == TIM_CHANNEL_1) || \
14059  ((CHANNEL) == TIM_CHANNEL_2))) \
14060  || \
14061  (((INSTANCE) == TIM10) && \
14062  (((CHANNEL) == TIM_CHANNEL_1))) \
14063  || \
14064  (((INSTANCE) == TIM11) && \
14065  (((CHANNEL) == TIM_CHANNEL_1))) \
14066  || \
14067  (((INSTANCE) == TIM12) && \
14068  (((CHANNEL) == TIM_CHANNEL_1) || \
14069  ((CHANNEL) == TIM_CHANNEL_2))) \
14070  || \
14071  (((INSTANCE) == TIM13) && \
14072  (((CHANNEL) == TIM_CHANNEL_1))) \
14073  || \
14074  (((INSTANCE) == TIM14) && \
14075  (((CHANNEL) == TIM_CHANNEL_1))))
14076 
14077 /************ TIM Instances : complementary output(s) available ***************/
14078 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14079  ((((INSTANCE) == TIM1) && \
14080  (((CHANNEL) == TIM_CHANNEL_1) || \
14081  ((CHANNEL) == TIM_CHANNEL_2) || \
14082  ((CHANNEL) == TIM_CHANNEL_3))) \
14083  || \
14084  (((INSTANCE) == TIM8) && \
14085  (((CHANNEL) == TIM_CHANNEL_1) || \
14086  ((CHANNEL) == TIM_CHANNEL_2) || \
14087  ((CHANNEL) == TIM_CHANNEL_3))))
14088 
14089 /****************** TIM Instances : supporting counting mode selection ********/
14090 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14091  ((INSTANCE) == TIM2) || \
14092  ((INSTANCE) == TIM3) || \
14093  ((INSTANCE) == TIM4) || \
14094  ((INSTANCE) == TIM5) || \
14095  ((INSTANCE) == TIM8))
14096 
14097 /****************** TIM Instances : supporting clock division *****************/
14098 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14099  ((INSTANCE) == TIM2) || \
14100  ((INSTANCE) == TIM3) || \
14101  ((INSTANCE) == TIM4) || \
14102  ((INSTANCE) == TIM5) || \
14103  ((INSTANCE) == TIM8) || \
14104  ((INSTANCE) == TIM9) || \
14105  ((INSTANCE) == TIM10)|| \
14106  ((INSTANCE) == TIM11)|| \
14107  ((INSTANCE) == TIM12)|| \
14108  ((INSTANCE) == TIM13)|| \
14109  ((INSTANCE) == TIM14))
14110 
14111 /****************** TIM Instances : supporting commutation event generation ***/
14112 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
14113  ((INSTANCE) == TIM8))
14114 
14115 
14116 /****************** TIM Instances : supporting OCxREF clear *******************/
14117 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14118  ((INSTANCE) == TIM2) || \
14119  ((INSTANCE) == TIM3) || \
14120  ((INSTANCE) == TIM4) || \
14121  ((INSTANCE) == TIM5) || \
14122  ((INSTANCE) == TIM8))
14123 
14124 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
14125 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14126  ((INSTANCE) == TIM2) || \
14127  ((INSTANCE) == TIM3) || \
14128  ((INSTANCE) == TIM4) || \
14129  ((INSTANCE) == TIM5) || \
14130  ((INSTANCE) == TIM8) || \
14131  ((INSTANCE) == TIM9) || \
14132  ((INSTANCE) == TIM12))
14133 
14134 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
14135 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14136  ((INSTANCE) == TIM2) || \
14137  ((INSTANCE) == TIM3) || \
14138  ((INSTANCE) == TIM4) || \
14139  ((INSTANCE) == TIM5) || \
14140  ((INSTANCE) == TIM8))
14141 
14142 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
14143 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14144  ((INSTANCE) == TIM2) || \
14145  ((INSTANCE) == TIM3) || \
14146  ((INSTANCE) == TIM4) || \
14147  ((INSTANCE) == TIM5) || \
14148  ((INSTANCE) == TIM8) || \
14149  ((INSTANCE) == TIM9) || \
14150  ((INSTANCE) == TIM12))
14151 
14152 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
14153 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14154  ((INSTANCE) == TIM2) || \
14155  ((INSTANCE) == TIM3) || \
14156  ((INSTANCE) == TIM4) || \
14157  ((INSTANCE) == TIM5) || \
14158  ((INSTANCE) == TIM8) || \
14159  ((INSTANCE) == TIM9) || \
14160  ((INSTANCE) == TIM12))
14161 
14162 /****************** TIM Instances : supporting repetition counter *************/
14163 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14164  ((INSTANCE) == TIM8))
14165 
14166 /****************** TIM Instances : supporting encoder interface **************/
14167 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14168  ((INSTANCE) == TIM2) || \
14169  ((INSTANCE) == TIM3) || \
14170  ((INSTANCE) == TIM4) || \
14171  ((INSTANCE) == TIM5) || \
14172  ((INSTANCE) == TIM8) || \
14173  ((INSTANCE) == TIM9) || \
14174  ((INSTANCE) == TIM12))
14175 /****************** TIM Instances : supporting Hall sensor interface **********/
14176 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14177  ((INSTANCE) == TIM2) || \
14178  ((INSTANCE) == TIM3) || \
14179  ((INSTANCE) == TIM4) || \
14180  ((INSTANCE) == TIM5) || \
14181  ((INSTANCE) == TIM8))
14182 /****************** TIM Instances : supporting the break function *************/
14183 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14184  ((INSTANCE) == TIM8))
14185 
14186 /******************** USART Instances : Synchronous mode **********************/
14187 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14188  ((INSTANCE) == USART2) || \
14189  ((INSTANCE) == USART3) || \
14190  ((INSTANCE) == USART6))
14191 
14192 /******************** UART Instances : Half-Duplex mode **********************/
14193 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14194  ((INSTANCE) == USART2) || \
14195  ((INSTANCE) == USART3) || \
14196  ((INSTANCE) == UART4) || \
14197  ((INSTANCE) == UART5) || \
14198  ((INSTANCE) == USART6))
14199 
14200 /* Legacy defines */
14201 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
14202 
14203 /****************** UART Instances : Hardware Flow control ********************/
14204 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14205  ((INSTANCE) == USART2) || \
14206  ((INSTANCE) == USART3) || \
14207  ((INSTANCE) == USART6))
14208 /******************** UART Instances : LIN mode **********************/
14209 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
14210 
14211 /********************* UART Instances : Smart card mode ***********************/
14212 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14213  ((INSTANCE) == USART2) || \
14214  ((INSTANCE) == USART3) || \
14215  ((INSTANCE) == USART6))
14216 
14217 /*********************** UART Instances : IRDA mode ***************************/
14218 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14219  ((INSTANCE) == USART2) || \
14220  ((INSTANCE) == USART3) || \
14221  ((INSTANCE) == UART4) || \
14222  ((INSTANCE) == UART5) || \
14223  ((INSTANCE) == USART6))
14224 
14225 
14226 /*********************** PCD Instances ****************************************/
14227 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
14228  ((INSTANCE) == USB_OTG_HS))
14229 
14230 /*********************** HCD Instances ****************************************/
14231 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
14232  ((INSTANCE) == USB_OTG_HS))
14233 
14234 /****************************** SDIO Instances ********************************/
14235 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
14236 
14237 /****************************** IWDG Instances ********************************/
14238 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14239 
14240 /****************************** WWDG Instances ********************************/
14241 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
14242 
14243 /****************************** USB Exported Constants ************************/
14244 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
14245 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
14246 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
14247 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
14248 
14249 /*
14250  * @brief Specific devices reset values definitions
14251  */
14252 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
14253 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
14254 
14255 #define RCC_MAX_FREQUENCY 168000000U
14256 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
14257 #define RCC_MAX_FREQUENCY_SCALE2 144000000U
14258 #define RCC_PLLVCO_OUTPUT_MIN 100000000U
14259 #define RCC_PLLVCO_INPUT_MIN 950000U
14260 #define RCC_PLLVCO_INPUT_MAX 2100000U
14261 #define RCC_PLLVCO_OUTPUT_MAX 432000000U
14263 #define RCC_PLLN_MIN_VALUE 50U
14264 #define RCC_PLLN_MAX_VALUE 432U
14265 
14266 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U
14267 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U
14268 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U
14269 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U
14270 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U
14272 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U
14273 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U
14274 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U
14275 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U
14277 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
14278 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
14279 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
14280 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
14281 /******************************************************************************/
14282 /* For a painless codes migration between the STM32F4xx device product */
14283 /* lines, the aliases defined below are put in place to overcome the */
14284 /* differences in the interrupt handlers and IRQn definitions. */
14285 /* No need to update developed interrupt code when moving across */
14286 /* product lines within the same STM32F4 Family */
14287 /******************************************************************************/
14288 /* Aliases for __IRQn */
14289 #define FMC_IRQn FSMC_IRQn
14290 
14291 /* Aliases for __IRQHandler */
14292 #define FMC_IRQHandler FSMC_IRQHandler
14293 
14306 #ifdef __cplusplus
14307 }
14308 #endif /* __cplusplus */
14309 
14310 #endif /* __STM32F405xx_H */
__IO
#define __IO
Definition: core_armv8mbl.h:196
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f405xx.h:66
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f405xx.h:74
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32f405xx.h:85
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32f405xx.h:90
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32f405xx.h:99
SDIO_IRQn
@ SDIO_IRQn
Definition: stm32f405xx.h:126
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32f405xx.h:80
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32f405xx.h:150
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32f405xx.h:133
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32f405xx.h:144
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f405xx.h:109
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f405xx.h:110
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f405xx.h:69
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f405xx.h:107
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f405xx.h:105
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32f405xx.h:145
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32f405xx.h:120
USART2_IRQn
@ USART2_IRQn
Definition: stm32f405xx.h:115
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32f405xx.h:136
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f405xx.h:72
ADC_IRQn
@ ADC_IRQn
Definition: stm32f405xx.h:95
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32f405xx.h:128
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f405xx.h:113
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32f405xx.h:132
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition: stm32f405xx.h:141
RCC_IRQn
@ RCC_IRQn
Definition: stm32f405xx.h:82
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32f405xx.h:131
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32f405xx.h:149
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f405xx.h:111
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32f405xx.h:123
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f405xx.h:71
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f405xx.h:75
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32f405xx.h:148
FSMC_IRQn
@ FSMC_IRQn
Definition: stm32f405xx.h:125
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32f405xx.h:147
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition: stm32f405xx.h:139
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f405xx.h:70
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f405xx.h:73
RNG_IRQn
@ RNG_IRQn
Definition: stm32f405xx.h:153
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f405xx.h:81
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32f405xx.h:143
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f405xx.h:77
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f405xx.h:108
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f405xx.h:106
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32f405xx.h:134
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition: stm32f405xx.h:96
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32f405xx.h:151
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32f405xx.h:88
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f405xx.h:117
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition: stm32f405xx.h:102
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f405xx.h:100
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32f405xx.h:89
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32f405xx.h:142
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32f405xx.h:119
FPU_IRQn
@ FPU_IRQn
Definition: stm32f405xx.h:154
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32f405xx.h:121
USART6_IRQn
@ USART6_IRQn
Definition: stm32f405xx.h:146
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f405xx.h:112
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32f405xx.h:152
PVD_IRQn
@ PVD_IRQn
Definition: stm32f405xx.h:78
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f405xx.h:103
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition: stm32f405xx.h:101
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition: stm32f405xx.h:140
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f405xx.h:83
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition: stm32f405xx.h:97
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f405xx.h:87
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32f405xx.h:135
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32f405xx.h:79
UART5_IRQn
@ UART5_IRQn
Definition: stm32f405xx.h:130
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32f405xx.h:93
USART1_IRQn
@ USART1_IRQn
Definition: stm32f405xx.h:114
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f405xx.h:86
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f405xx.h:68
UART4_IRQn
@ UART4_IRQn
Definition: stm32f405xx.h:129
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f405xx.h:122
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f405xx.h:84
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32f405xx.h:137
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32f405xx.h:127
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32f405xx.h:124
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32f405xx.h:92
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32f405xx.h:94
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f405xx.h:104
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition: stm32f405xx.h:138
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32f405xx.h:98
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32f405xx.h:91
USART3_IRQn
@ USART3_IRQn
Definition: stm32f405xx.h:116
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f405xx.h:118
ADC_Common_TypeDef
Definition: stm32f405xx.h:200
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f405xx.h:202
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32f405xx.h:203
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f405xx.h:201
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f405xx.h:176
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f405xx.h:183
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f405xx.h:192
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f405xx.h:186
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f405xx.h:185
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f405xx.h:188
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f405xx.h:194
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:196
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f405xx.h:182
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f405xx.h:184
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f405xx.h:181
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f405xx.h:191
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f405xx.h:195
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f405xx.h:190
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f405xx.h:187
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f405xx.h:189
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f405xx.h:178
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f405xx.h:193
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:177
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f405xx.h:180
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f405xx.h:179
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:225
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f405xx.h:226
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f405xx.h:229
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f405xx.h:227
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f405xx.h:228
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:237
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f405xx.h:239
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f405xx.h:238
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:213
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f405xx.h:214
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f405xx.h:217
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f405xx.h:216
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f405xx.h:215
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:247
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f405xx.h:252
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f405xx.h:260
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f405xx.h:248
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f405xx.h:254
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f405xx.h:262
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f405xx.h:255
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f405xx.h:253
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f405xx.h:250
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f405xx.h:261
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f405xx.h:263
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f405xx.h:267
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f405xx.h:266
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f405xx.h:251
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f405xx.h:249
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f405xx.h:265
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f405xx.h:264
CRC_TypeDef
CRC calculation unit.
Definition: stm32f405xx.h:277
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:278
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f405xx.h:279
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f405xx.h:281
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f405xx.h:280
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:282
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:290
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f405xx.h:299
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f405xx.h:297
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f405xx.h:298
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f405xx.h:296
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f405xx.h:292
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f405xx.h:301
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f405xx.h:302
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:291
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f405xx.h:303
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f405xx.h:293
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f405xx.h:300
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f405xx.h:295
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f405xx.h:294
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:304
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f405xx.h:312
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f405xx.h:313
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f405xx.h:316
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f405xx.h:315
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:314
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f405xx.h:325
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f405xx.h:331
DMA_Stream_TypeDef::M0AR
__IO uint32_t M0AR
Definition: stm32f405xx.h:329
DMA_Stream_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:326
DMA_Stream_TypeDef::M1AR
__IO uint32_t M1AR
Definition: stm32f405xx.h:330
DMA_Stream_TypeDef::PAR
__IO uint32_t PAR
Definition: stm32f405xx.h:328
DMA_Stream_TypeDef::NDTR
__IO uint32_t NDTR
Definition: stm32f405xx.h:327
DMA_TypeDef
Definition: stm32f405xx.h:335
DMA_TypeDef::LISR
__IO uint32_t LISR
Definition: stm32f405xx.h:336
DMA_TypeDef::HISR
__IO uint32_t HISR
Definition: stm32f405xx.h:337
DMA_TypeDef::LIFCR
__IO uint32_t LIFCR
Definition: stm32f405xx.h:338
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
Definition: stm32f405xx.h:339
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f405xx.h:347
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f405xx.h:350
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f405xx.h:349
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f405xx.h:352
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f405xx.h:351
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f405xx.h:348
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f405xx.h:353
FLASH_TypeDef
FLASH Registers.
Definition: stm32f405xx.h:361
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition: stm32f405xx.h:368
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f405xx.h:363
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f405xx.h:362
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:366
FLASH_TypeDef::OPTCR
__IO uint32_t OPTCR
Definition: stm32f405xx.h:367
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:365
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f405xx.h:364
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f405xx.h:378
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f405xx.h:387
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f405xx.h:396
FSMC_Bank2_3_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f405xx.h:402
FSMC_Bank2_3_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f405xx.h:399
FSMC_Bank2_3_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f405xx.h:404
FSMC_Bank2_3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f405xx.h:410
FSMC_Bank2_3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f405xx.h:405
FSMC_Bank2_3_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f405xx.h:398
FSMC_Bank2_3_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f405xx.h:400
FSMC_Bank2_3_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f405xx.h:397
FSMC_Bank2_3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f405xx.h:408
FSMC_Bank2_3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f405xx.h:407
FSMC_Bank2_3_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f405xx.h:403
FSMC_Bank2_3_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f405xx.h:409
FSMC_Bank2_3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f405xx.h:406
FSMC_Bank2_3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f405xx.h:401
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f405xx.h:418
FSMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f405xx.h:419
FSMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f405xx.h:421
FSMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f405xx.h:420
FSMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f405xx.h:422
FSMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f405xx.h:423
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f405xx.h:431
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f405xx.h:439
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f405xx.h:432
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f405xx.h:434
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f405xx.h:436
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f405xx.h:433
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f405xx.h:435
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f405xx.h:437
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f405xx.h:438
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f405xx.h:461
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f405xx.h:464
I2C_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:466
I2C_TypeDef::TRISE
__IO uint32_t TRISE
Definition: stm32f405xx.h:470
I2C_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f405xx.h:469
I2C_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f405xx.h:468
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f405xx.h:462
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f405xx.h:465
I2C_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32f405xx.h:467
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f405xx.h:463
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f405xx.h:478
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f405xx.h:479
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f405xx.h:481
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:482
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f405xx.h:480
PWR_TypeDef
Power Control.
Definition: stm32f405xx.h:491
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f405xx.h:493
PWR_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:492
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f405xx.h:501
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f405xx.h:527
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32f405xx.h:513
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f405xx.h:504
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32f405xx.h:508
RCC_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32f405xx.h:521
RCC_TypeDef::PLLI2SCFGR
__IO uint32_t PLLI2SCFGR
Definition: stm32f405xx.h:531
RCC_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32f405xx.h:522
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32f405xx.h:506
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f405xx.h:516
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32f405xx.h:514
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32f405xx.h:507
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f405xx.h:510
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f405xx.h:528
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f405xx.h:505
RCC_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32f405xx.h:520
RCC_TypeDef::SSCGR
__IO uint32_t SSCGR
Definition: stm32f405xx.h:530
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f405xx.h:511
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:502
RCC_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32f405xx.h:525
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f405xx.h:523
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f405xx.h:517
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f405xx.h:518
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32f405xx.h:515
RCC_TypeDef::APB1LPENR
__IO uint32_t APB1LPENR
Definition: stm32f405xx.h:524
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32f405xx.h:503
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f405xx.h:509
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:688
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:691
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:689
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:690
RTC_TypeDef
Real-Time Clock.
Definition: stm32f405xx.h:539
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f405xx.h:552
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f405xx.h:563
RTC_TypeDef::TAFCR
__IO uint32_t TAFCR
Definition: stm32f405xx.h:556
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f405xx.h:554
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f405xx.h:566
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f405xx.h:551
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32f405xx.h:577
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f405xx.h:567
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f405xx.h:555
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:541
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f405xx.h:560
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f405xx.h:548
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32f405xx.h:579
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f405xx.h:558
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f405xx.h:557
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f405xx.h:549
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f405xx.h:540
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32f405xx.h:578
RTC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32f405xx.h:559
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f405xx.h:569
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f405xx.h:573
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f405xx.h:572
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f405xx.h:550
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f405xx.h:562
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f405xx.h:570
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f405xx.h:564
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f405xx.h:543
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:542
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f405xx.h:565
RTC_TypeDef::CALIBR
__IO uint32_t CALIBR
Definition: stm32f405xx.h:546
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f405xx.h:553
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f405xx.h:547
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f405xx.h:568
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f405xx.h:545
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f405xx.h:574
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f405xx.h:571
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f405xx.h:544
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32f405xx.h:576
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f405xx.h:561
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f405xx.h:575
SDIO_TypeDef
SD host Interface.
Definition: stm32f405xx.h:587
SDIO_TypeDef::FIFOCNT
__IO const uint32_t FIFOCNT
Definition: stm32f405xx.h:605
SDIO_TypeDef::STA
__IO const uint32_t STA
Definition: stm32f405xx.h:601
SDIO_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32f405xx.h:590
SDIO_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f405xx.h:602
SDIO_TypeDef::RESPCMD
__IO const uint32_t RESPCMD
Definition: stm32f405xx.h:592
SDIO_TypeDef::DCOUNT
__IO const uint32_t DCOUNT
Definition: stm32f405xx.h:600
SDIO_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32f405xx.h:597
SDIO_TypeDef::RESP3
__IO const uint32_t RESP3
Definition: stm32f405xx.h:595
SDIO_TypeDef::RESP2
__IO const uint32_t RESP2
Definition: stm32f405xx.h:594
SDIO_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32f405xx.h:603
SDIO_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32f405xx.h:598
SDIO_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32f405xx.h:588
SDIO_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32f405xx.h:607
SDIO_TypeDef::RESP1
__IO const uint32_t RESP1
Definition: stm32f405xx.h:593
SDIO_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32f405xx.h:599
SDIO_TypeDef::RESP4
__IO const uint32_t RESP4
Definition: stm32f405xx.h:596
SDIO_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32f405xx.h:589
SDIO_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32f405xx.h:591
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f405xx.h:615
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f405xx.h:621
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:619
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f405xx.h:623
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f405xx.h:616
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f405xx.h:622
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f405xx.h:624
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f405xx.h:620
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:618
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f405xx.h:617
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f405xx.h:448
SYSCFG_TypeDef::CMPCR
__IO uint32_t CMPCR
Definition: stm32f405xx.h:453
SYSCFG_TypeDef::PMC
__IO uint32_t PMC
Definition: stm32f405xx.h:450
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32f405xx.h:449
TIM_TypeDef
TIM.
Definition: stm32f405xx.h:633
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f405xx.h:637
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f405xx.h:641
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f405xx.h:642
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f405xx.h:639
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f405xx.h:649
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f405xx.h:636
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f405xx.h:651
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f405xx.h:643
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f405xx.h:654
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f405xx.h:650
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f405xx.h:644
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f405xx.h:646
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f405xx.h:634
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f405xx.h:653
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f405xx.h:648
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f405xx.h:647
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f405xx.h:640
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f405xx.h:645
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f405xx.h:652
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:638
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f405xx.h:635
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f405xx.h:662
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f405xx.h:665
USART_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:664
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f405xx.h:669
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f405xx.h:666
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f405xx.h:668
USART_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:663
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f405xx.h:667
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f405xx.h:723
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32f405xx.h:739
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32f405xx.h:729
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32f405xx.h:732
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32f405xx.h:743
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f405xx.h:727
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32f405xx.h:731
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32f405xx.h:728
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32f405xx.h:730
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition: stm32f405xx.h:733
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32f405xx.h:726
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32f405xx.h:737
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32f405xx.h:724
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32f405xx.h:740
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32f405xx.h:741
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32f405xx.h:736
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32f405xx.h:735
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32f405xx.h:725
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32f405xx.h:738
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32f405xx.h:734
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f405xx.h:698
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32f405xx.h:707
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32f405xx.h:702
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32f405xx.h:708
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32f405xx.h:699
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32f405xx.h:705
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32f405xx.h:713
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32f405xx.h:710
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32f405xx.h:715
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32f405xx.h:709
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32f405xx.h:706
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32f405xx.h:704
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32f405xx.h:701
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32f405xx.h:703
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32f405xx.h:700
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32f405xx.h:712
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f405xx.h:793
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32f405xx.h:796
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32f405xx.h:794
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32f405xx.h:795
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32f405xx.h:798
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32f405xx.h:797
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32f405xx.h:799
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f405xx.h:779
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32f405xx.h:781
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32f405xx.h:784
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32f405xx.h:786
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32f405xx.h:782
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32f405xx.h:785
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32f405xx.h:780
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32f405xx.h:783
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f405xx.h:750
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32f405xx.h:756
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32f405xx.h:755
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f405xx.h:754
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32f405xx.h:757
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32f405xx.h:753
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32f405xx.h:758
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32f405xx.h:751
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f405xx.h:752
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f405xx.h:765
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f405xx.h:769
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32f405xx.h:770
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32f405xx.h:771
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32f405xx.h:766
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f405xx.h:767
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32f405xx.h:768
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f405xx.h:677
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:678
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f405xx.h:679
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:680
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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